Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-speed knots in the hourglass shaped planetary nebula Hubble 12

We present a detailed kinematical analysis of the young compact hourglass-shaped planetary nebula Hb 12. We performed optical imaging and long-slit spectroscopy of Hb 12 using the Manchester echelle spectrometer with the 2.1-m San Pedro Mártir telescope. We reveal, for the first time, the presence of end caps (or knots) aligned with the bipolar lobes of the planetary nebula shell in a deep [NII] ?6584 image of Hb 12. We measured from our spectroscopy radial velocities of ~120kms-1 for these knots. We have derived the inclination angle of the hourglass-shaped nebular shell to be ~65° to the line of sight. It has been suggested that Hb 12's central star system is an eclipsing binary which would imply a binary inclination of at least 80°. However, if the central binary has been the major shaping influence on the nebula, then both nebula and binary would be expected to share a common inclination angle. Finally, we report the discovery of high-velocity knots with Hubble-type velocities, close to the core of Hb 12, observed in Ha and oriented in the same direction as the end caps. Very different velocities and kinematical ages were calculated for the outer and inner knots showing that they may originate from different outburst events.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.