External circuit system effects on chlorine plasma instabilities

The effects of the external circuit on plasma instabilities in all inductive plasma source are investigated. The instabilities are found to be asymmetric with respect to the circuit input impedance. A simplified model of the antenna-plasnia coupling provides an explanation of the asymetry.

Control of leaky-mode propagation and radiation properties in hybrid dielectric-waveguide printed-circuit technology: Experimental results

Experimental results are presented to show how a planar circuit, printed on a laterally shielded dielectric waveguide, can induce and control the radiation from a leaky-mode. By studying the leaky-mode complex propagation constant, a desired radiation pattern can be synthesized, controlling the main radiation characteristics (pointing direction, beamwidth, sidelobes level) for a given frequency, This technique leads to very flexible and original leaky-wave antenna designs. The experiments show to be in very good agreement with the leaky-mode theory.

High-performance IQ modulator-based phase conjugator for modular retrodirective antenna array implementation

In this paper, we verify a new phase conjugating architecture suitable for deployment as (lie core building block in retrodirective antenna arrays, which can be scaled to any number of elements in a modular way without impacting on complexity. Our solution is based on a modified in-phase and quadrature modulator architecture, which completely resolves four major shortcomings of the conventional mixer-based approach currently used for the synthesis of phase conjugated energy derived from a sampled incoming wavefront. 1) The architecture presented removes the need for a local oscillator running at twice the RF signal frequency to be conjugated. 2) It maintains a constant transmit power even if receive power goes as low as -120 dBm. 3) All unwanted re-transmit signal products are suppressed by at least 40 dB. 4) The issue of poor RF-IF leakage prevalent in mixer-based phase-conjugation solutions is completely mitigated. The circuit has also been shown to have high conjugation accuracy (better than +/-1 degrees at -60-dBm input). Near theoretically perfect experimental monostatic and bistatic results are presented for a ten-element retrodirective array constructed using the new phase conjugation architecture.

Current transients in the small salient-pole alternator caused by sudden short-circuit and synchronisation events

Small salient-pole machines, in the range 30 kVA to 2 MVA, are often used in distributed generators, which in turn are likely to form the major constituent of power generation in power system islanding schemes or microgrids. In addition to power system faults, such as short-circuits, islanding contains an inherent risk of out-of-synchronism re-closure onto the main power system. To understand more fully the effect of these phenomena on a small salient-pole alternator, the armature and field currents from tests conducted on a 31.5 kVA machine are analysed. This study demonstrates that by resolving the voltage difference between the machine terminals and bus into direct and quadrature axis components, interesting properties of the transient currents are revealed. The presence of saliency and short time-constants cause intriguing differences between machine events such as out-of-phase synchronisations and sudden three-phase short-circuits.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.