Simulation and life cycle assessment of process design alternatives for biodiesel production from waste vegetable oils

This study uses the process simulator ASPEN Plus and Life Cycle Assessment (LCA) to compare three process design alternatives for biodiesel production from waste vegetable oils that are: the conventional alkali-catalyzed process including a free fatty acids (FFAs) pre-treatment, the acid-catalyzed process, and the supercritical methanol process using propane as co-solvent. Results show that the supercritical methanol process using propane as co-solvent is the most environmentally favorable alternative. Its smaller steam consumption in comparison with the other process design alternatives leads to a lower contribution to the potential environmental impacts (PEI’s). The acid-catalyzed process generally shows the highest PEI’s, in particular due to the high energy requirements associated with methanol recovery operations.

Comparison of allocation approaches in soybean biodiesel life cycle assessment

This work shows the influence of using different allocation approaches when modelling the inventory analysis in a soybean biodiesel life cycle assessment (LCA). Results obtained using mass, energy and economic based allocations are compared, focusing on the following aspects: normalised potential environmental impact (PEI) categories, total PEI and relative contributions to the total PEI from each life cycle stage and environmental impact category. Similar results are obtained either using economic and energy based allocations. However, different results are obtained when mass based allocation is used when compared with the other two. This study also illustrates that using different allocation approaches in biodiesel LCA may influence the final conclusions, especially in comparative assertions, emphasising the need to perform a sensitivity analysis in the LCA interpretation step.

A few what-ifs on using statistical analysis of stochastic simulation runs to extract timeliness properties

Modern real-time systems, with a more flexible and adaptive nature, demand approaches for timeliness evaluation based on probabilistic measures of meeting deadlines. In this context, simulation can emerge as an adequate solution to understand and analyze the timing behaviour of actual systems. However, care must be taken with the obtained outputs under the penalty of obtaining results with lack of credibility. Particularly important is to consider that we are more interested in values from the tail of a probability distribution (near worst-case probabilities), instead of deriving confidence on mean values. We approach this subject by considering the random nature of simulation output data. We will start by discussing well known approaches for estimating distributions out of simulation output, and the confidence which can be applied to its mean values. This is the basis for a discussion on the applicability of such approaches to derive confidence on the tail of distributions, where the worst-case is expected to be.

Cycle time properties of the PROFIBUS timed-token protocol

A recent trend in distributed computer-controlled systems (DCCS) is to interconnect the distributed computing elements by means of multi-point broadcast networks. Since the network medium is shared between a number of network nodes, access contention exists and must be solved by a medium access control (MAC) protocol. Usually, DCCS impose real-time constraints. In essence, by real-time constraints we mean that traffic must be sent and received within a bounded interval, otherwise a timing fault is said to occur. This motivates the use of communication networks with a MAC protocol that guarantees bounded access and response times to message requests. PROFIBUS is a communication network in which the MAC protocol is based on a simplified version of the timed-token protocol. In this paper we address the cycle time properties of the PROFIBUS MAC protocol, since the knowledge of these properties is of paramount importance for guaranteeing the real-time behaviour of a distributed computer-controlled system which is supported by this type of network.

Sporadic multiprocessor scheduling with few preemptions

Consider the problem of scheduling n sporadic tasks so as to meet deadlines on m identical processors. A task is characterised by its minimum interarrival time and its worst-case execution time. Tasks are preemptible and may migrate between processors. We propose an algorithm with limited migration, configurable for a utilisation bound of 88% with few preemptions (and arbitrarily close to 100% with more preemptions).

Impacto dos sistemas colaborativos nas organizações: estudo de casos de adopção e utilização de sistemas workflow

Dissertação apresentada na Universidade do Minho com vista à obtenção do grau de Doutor em Tecnologias e Sistemas de Informação (Engenharia e Gestão de Sistemas de Informação)

Multiprocessor scheduling with few preemptions

Consider the problem of scheduling a set of periodically arriving tasks on a multiprocessor with the goal of meeting deadlines. Processors are identical and have the same speed. Tasks can be preempted and they can migrate between processors. We propose an algorithm with a utilization bound of 66% and with few preemptions. It can trade a higher utilization bound for more preemption and in doing so it has a utilization bound of 100%.

Multilevel high-voltage pulse generation based on a new modular solid-state switch

This paper describes a modular solid-state switching cell derived from the Marx generator concept to be used in topologies for generating multilevel unipolar and bipolar high-voltage (HV) pulses into resistive loads. The switching modular cell comprises two ON/OFF semiconductors, a diode, and a capacitor. This cell can be stacked, being the capacitors charged in series and their voltages balanced in parallel. To balance each capacitor voltage without needing any parameter measurement, a vector decision diode algorithm is used in each cell to drive the two switches. Simulation and experimental results, for generating multilevel unipolar and bipolar HV pulses into resistive loads are presented.

FEW phone file system

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

O teatro como eixo curricular de desenvolvimento de competências no 1.º ciclo

Relatório Final apresentado à Escola Superior de Educação de Lisboa para obtenção de grau de mestre em Ensino no 1º e no 2º Ciclos do Ensino Básico

Generic life cycle assessment of the Jatropha biodiesel system

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Energia e Bioenergia

IVA : o regime de contabilidade de caixa e o ciclo de caixa das empresas

Mestrado em Fiscalidade

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.

A CMOS variable width short-pulse generator circuit for UWB RADAR applications

IEEE International Symposium on Circuits and Systems, pp. 2713 – 2716, Seattle, EUA

Age constraints on the late cretaceous alkaline magmatism on the West Iberian margin

Cretaceous Research 30 (2009) 575–586