Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

On-line self-healing of circuits implemented on reconfigurable FPGAs

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Is ambient intelligence a truly human-centric paradigm in industry? Current research and application scenario

Based on the paper presented at the International Conference “Autonomous Systems: inter-relations of technical and societal issues”, organized by IET with the support of the Portuguese-German collaboration project on “Technology Assessment of Autonomous Robotics” (DAAD/CRUP) at FCT-UNL, Biblioteca da UNL, Campus de Caparica on 5-6 November 2009.

Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores

Federação Portuguesa de Basquetebol: proposta de comunicação estratégica para o basquetebol em Portugal

Trabalho de projeto apresentado à Escola Superior de Comunicação Social como parte dos requisitos para obtenção de grau de mestre em Gestão Estratégica das Relações Públicas.

Confronting predictive texture zeros in lepton mass matrices with current data

Several popular Ansatze of lepton mass matrices that contain texture zeros are confronted with current neutrino observational data. We perform a systematic chi(2) analysis in a wide class of schemes, considering arbitrary Hermitian charged-lepton mass matrices and symmetric mass matrices for Majorana neutrinos or Hermitian mass matrices for Dirac neutrinos. Our study reveals that several patterns are still consistent with all the observations at the 68.27% confidence level, while some others are disfavored or excluded by the experimental data. The well-known Frampton-Glashow-Marfatia two-zero textures, hybrid textures, and parallel structures (among others) are considered.

Reversible current power supply for fast-field cycling nuclear magnetic resonance equipment

The Fast Field-Cycling Nuclear Magnetic Resonance (FFC-NMR) is a technique used to study the molecular dynamics of different types of materials. The main elements of this equipment are a magnet and its power supply. The magnet used as reference in this work is basically a ferromagnetic core with two sets of coils and an air-gap where the materials' sample is placed. The power supply should supply the magnet being the magnet current controlled in order to perform cycles. One of the technical issues of this type of solution is the compensation of the non-linearities associated to the magnetic characteristic of the magnet and to parasitic magnetic fields. To overcome this problem, this paper describes and discusses a solution for the FFC-NMR power supply based on a four quadrant DC/DC converter.

Diagnosis of an EPS module

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores

Análise de Desempenho e Recomendação para Soluções IVR

Mestrado em Engenharia Informática, Área de Especialização em Tecnologias do Conhecimento e da Decisão

SI SC MDAC switched current-capacitor multiplying digital-to-analog converter

Dissertação apresentada para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Melhoria do Processo Produtivo da Pietec Através das Ferramentas Kaizen

Esta Tese de Mestrado foi realizada na empresa Pietec Cortiças S.A.. A empresa Pietec Cortiças S.A. é a unidade industrial responsável pela produção de rolhas técnicas de cortiça do Grupo Piedade. O objetivo desta tese prende-se com a melhoria do processo produtivo de uma das suas secções, a secção da Marcação. Esta secção é responsável pela marcação da superfície da rolha, pela aplicação do tratamento de superfície e pelo embalamento das rolhas. A otimização do processo da secção de Marcação, na qualidade de última secção do processo produtivo, permitirá à empresa obter vantagens competitivas. De forma a atingir o objetivo proposto, foi realizado um levantamento exaustivo do processo produtivo e das respetivas operações. Esta análise permitiu a identificação dos possíveis pontos de desperdício, a sua avaliação e a definição de possíveis melhorias que visam o aumento de produtividade e a redução do número de produtos não conformes. Uma vez identificados os pontos críticos do processo, procedeu-se à definição das ações de melhoria a implementar de forma a melhorar o processo produtivo. As ações tomadas assentam na filosofia Lean e nos seus princípios, utilizando-se algumas das ferramentas desta filosofia para concretizar os objetivos traçados. A ferramenta de análise Plan-Do-Check-Act (PDCA) foi a ferramenta base do projeto, acompanhando na elaboração do plano de ação, na implementação das ferramentas 5S e Single Minute Exchange of Die (SMED), na verificação dos resultados e no plano de manutenção das melhorias alcançadas. Após a implementação das medidas definidas no processo de marcação da superfície das rolhas, foi mensurada uma melhoria de 23 % no tempo médio de setup da máquina de marcação. Esta melhoria global foi alcançada através de intervenções no processo de vazamento do circuito da máquina de marcação, no procedimento de armazenamento dos moldes de marcação e na alteração dos mecanismos de ajuste da máquina de marcar e de orientar. No processo de embalamento das rolhas, as medidas implementadas produziram um aumento de 1,7 % no número de rolhas produzidas e uma redução do número de rolhas não conformes de 3,6 %. Os resultados obtidos no projeto demonstram que é possível continuar a melhorar o estado atual dos processos. Constatou-se ainda que, com a adoção de ferramentas de análise e de proposta de melhoria adequadas, é possível atuar sobre os processos e obter melhorias a curto prazo, sem que para isso seja necessário efetuar grandes investimentos.