ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction

The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms. An implementation of this architecture could migrate a null thread in 66 cycles -- over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar, and scales linearly with data block size. Since the performance of the migration mechanism is on par with that of an L2 cache, the implementation simulated in my work has no data caches and relies instead on multithreading and the migration mechanism to hide and reduce access latencies.

Research in Architecture: Looking Backward and Forward: Forty-Year Experience in Architectural Research at the Faculty of Architecture STU

The introduction of my contribution contains a brief information on the Faculty of Architecture of the Slovak University of Technology in Bratislava (FA STU) and the architectural research performed at this institution. Schemes and priorities of our research in architecture have changed several times since the very beginning in early 50’s. The most significant change occurred after “the velvet revolution” in 1989. Since 1990 there have been several sources to support research at universities. The significant part of my contribution is rooted in my own research experience since the time I had joined FA STU in 1975 as a young architect and researcher. The period of the 80’s is characterized by the first unintentional attempts to do “research by design” and my “scientific” achievements as by-products of my design work. Some of them resulted in the following issues: conception of mezzo-space, theory of the complex perception of architectural space and definition of basic principles of ecologically conscious architecture. Nowadays I continue my research by design within the application of so called solar envelope in urban scale with my students.

Design of highly parallel architecture with Alpha and Handel

We propose a bridge between two important parallel programming paradigms: data parallelism and communicating sequential processes (CSP). Data parallel pipelined architectures obtained with the Alpha language can be embedded in a control intensive application expressed in CSP-based Handel formalism. The interface is formally defined from the semantics of the languages Alpha and Handel. This work will ease the design of compute intensive applications on FPGAs.

Parallel pipelined histogram architecture via c-slow retiming

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy.

The potential of the 3-UPU translational parallel manipulator and a procedure to select the best architecture

The 3-UPU three degrees of freedom fully parallel manipulator, where U and P are for universal and prismatic pair respectively, is a very well known manipulator that can provide the platform with three degrees of freedom of pure translation, pure rotation or mixed translation and rotation with respect to the base, according to the relative directions of the revolute pair axes (each universal pair comprises two revolute pairs with intersecting and perpendicular axes). In particular, pure translational parallel 3-UPU manipulators (3-UPU TPMs) received great attention. Many studies have been reported in the literature on singularities, workspace, and joint clearance influence on the platform accuracy of this manipulator. However, much work has still to be done to reveal all the features this topology can offer to the designer when different architecture, i.e. different geometry are considered. Therefore, this dissertation will focus on this type of the 3-UPU manipulators. The first part of the dissertation presents six new architectures of the 3-UPU TPMs which offer interesting features to the designer. In the second part, a procedure is presented which is based on some indexes, in order to allows the designer to select the best architecture of the 3-UPU TPMs for a given task. Four indexes are proposed as stiffness, clearance, singularity and size of the manipulator in order to apply the procedure.

A Hierarchical Architecture with Parallel Comunication for Implementing P Systems

Membrane systems are computational equivalent to Turing machines. However, its distributed and massively parallel nature obtain polynomial solutions opposite to traditional non-polynomial ones. Nowadays, developed investigation for implementing membrane systems has not yet reached the massively parallel character of this computational model. Better published approaches have achieved a distributed architecture denominated “partially parallel evolution with partially parallel communication” where several membranes are allocated at each processor, proxys are used to communicate with membranes allocated at different processors and a policy of access control to the communications is mandatory. With these approaches, it is obtained processors parallelism in the application of evolution rules and in the internal communication among membranes allocated inside each processor. Even though, external communications share a common communication line, needed for the communication among membranes arranged in different processors, are sequential. In this work, we present a new hierarchical architecture that reaches external communication parallelism among processors and substantially increases parallelization in the application of evolution rules and internal communications. Consequently, necessary time for each evolution step is reduced. With all of that, this new distributed hierarchical architecture is near to the massively parallel character required by the model.

Parallel relationships, architecture and water : the urban spa

This thesis explores the relationship of architecture and water through the design of an urban spa that offers both a bodily and a poetic experience of water. Research included investigation of recent architectural projects that enhance and order the view, sound, and touch of water as well as projects that integrate fountains, showers and reflecting pools into the experience of a building. In the design of the spa, the movement of water was based metaphorically on the natural water cycle: evaporation, condensation and collection of water in pools. The building presents fountains, rivulets, and pools in a descending sequence that represents the natural flow of water. The temperature of water and the activities of the spa follow the same descending sequence, progressing from a warm water bath at the top of the building to cool swimming pool at the plaza level in a contemporary interpretation of the experience of a Roman Bath.

Parallel pipelined histogram architecture via C-slow retiming

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

Integrating Architecture for a Live-Work Lifestyle

Urban centers all around the world are striving to re-orient themselves to promoting ideals of human engagement, flexibility, openness and synergy, that thoughtful architecture can provide. From a time when solitude in one’s own backyard was desirable, today’s outlook seeks more, to cater to the needs of diverse individuals and that of collaborators. This thesis is an investigation of the role of architecture in realizing how these ideals might be achieved, using Mixed Use Developments as the platform of space to test these designs ideas on. The author also investigates, identifies, and re-imagines how the idea of live-work excites and attracts users and occupants towards investing themselves in Mixed Used Developments (MUD’s), in urban cities. On the premise that MUDs historically began with an intention of urban revitalization, lying in the core of this spatial model, is the opportunity to investigate what makes mixing of uses an asset, especially in the eyes to today’s generation. Within the framework of reference to the current generation, i.e. the millennial population and alike, who have a lifestyle core that is urban-centric, the excitement for this topic is in the vision of MUD’s that will spatially cater to a variety in lifestyles, demographics, and functions, enabling its users to experience a vibrant 24/7 destination. Where cities are always in flux, the thesis will look to investigate the idea of opportunistic space, in a new MUD, that can also be perceived as an adaptive reuse of itself. The sustainability factor lies in the foresight of the transformative and responsive character of the different uses in the MUD at large, which provides the possibility to cater to a changing demand of building use over time. Delving into the architectural response, the thesis in the process explores, conflicts, tensions, and excitements, and the nature of relationships between different spatial layers of permanence vs. transformative, public vs. private, commercial vs. residential, in such an MUD. At a larger scale, investigations elude into the formal meaning and implications of the proposed type of MUD’s and the larger landscapes in which they are situated, with attempts to blur the fine line between architecture and urbanism. A unique character of MUD’s is the power it has to draw in people at the ground level and lead them into exciting spatial experiences. While the thesis stemmed from a purely objective and theoretical standpoint, the author believes that it is only when context is played into the design thinking process, that true architecture may start to flourish. The unique The significance of this thesis lies on the premise that the author believes that this re-imagined MUD has immense opportunity to amplify human engagement with designed space, and in the belief that it will better enable fostering sustainable communities and in the process, enhance people’s lives.

Specification of software architecture reconfiguration

In the past years, Software Architecture has attracted increased attention by academia and industry as the unifying concept to structure the design of complex systems. One particular research area deals with the possibility of reconfiguring architectures to adapt the systems they describe to new requirements. Reconfiguration amounts to adding and removing components and connections, and may have to occur without stopping the execution of the system being reconfigured. This work contributes to the formal description of such a process. Taking as a premise that a single formalism hardly ever satisfies all requirements in every situation, we present three approaches, each one with its own assumptions about the systems it can be applied to and with different advantages and disadvantages. Each approach is based on work of other researchers and has the aesthetic concern of changing as little as possible the original formalism, keeping its spirit. The first approach shows how a given reconfiguration can be specified in the same manner as the system it is applied to and in a way to be efficiently executed. The second approach explores the Chemical Abstract Machine, a formalism for rewriting multisets of terms, to describe architectures, computations, and reconfigurations in a uniform way. The last approach uses a UNITY-like parallel programming design language to describe computations, represents architectures by diagrams in the sense of Category Theory, and specifies reconfigurations by graph transformation rules.

Supporting real-time parallel task models with work-stealing

Dynamic parallel scheduling using work-stealing has gained popularity in academia and industry for its good performance, ease of implementation and theoretical bounds on space and time. Cores treat their own double-ended queues (deques) as a stack, pushing and popping threads from the bottom, but treat the deque of another randomly selected busy core as a queue, stealing threads only from the top, whenever they are idle. However, this standard approach cannot be directly applied to real-time systems, where the importance of parallelising tasks is increasing due to the limitations of multiprocessor scheduling theory regarding parallelism. Using one deque per core is obviously a source of priority inversion since high priority tasks may eventually be enqueued after lower priority tasks, possibly leading to deadline misses as in this case the lower priority tasks are the candidates when a stealing operation occurs. Our proposal is to replace the single non-priority deque of work-stealing with ordered per-processor priority deques of ready threads. The scheduling algorithm starts with a single deque per-core, but unlike traditional work-stealing, the total number of deques in the system may now exceed the number of processors. Instead of stealing randomly, cores steal from the highest priority deque.

Work-in-progress on a thin IEEE1451.0 - architecture to implement reconfigurable Weblab infrastructures

Institutions have been creating their own specific weblab infrastructures. Usually, they use distinct software and hardware architectures comprehending instruments and modules (I&M) able to be parameterized but difficult to be shared. These aspects are impairing their widespread in education, since collaboration between institutions, in developing and sharing resources, is still low. To handle both aspects, this paper proposes the adoption of the IEEE1451.0 Std. with FPGA technology for creating reconfigurable weblab infrastructures. It is suggested the adoption of an IEEE1451.0 infrastructure with compatible instruments, described in Hardware Description Languages (HDL), to be reconfigured in FPGA-based boards. Besides an overview of the IEEE1451.0 Std., this paper presents a solution currently under development which seeks to enable the reconfiguration and the remote control of weblab infrastructures using a set of IEEE1451.0 HTTP commands.