Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

One-transistor floating-body random access memory retention time distribution is investigated on silicon-on-insulator UTBOX devices. It is shown that the average retention time can be improved by two to three orders of magnitude by reducing the body-junction electric field. However, the retention time distribution, which is mainly caused by the generation-recombination center density variation, remains similar.

Dependence of Generation-Recombination Noise With Gate Voltage in FD SOI MOSFETs

A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.

Reduced-order modelling, circuit-level design and SOI fabrication of microelectromechanical resonators

This thesis deals with two important research aspects concerning radio frequency (RF) microresonators and switches. First, a new approach for compact modeling and simulation of these devices is presented. Then, a combined process flow for their simultaneous fabrication on a SOI substrate is proposed. Compact models for microresonators and switches are extracted by applying mathematical model order reduction (MOR) to the devices finite element (FE) description in ANSYS c° . The behaviour of these devices includes forms of nonlinearities. However, an approximation in the creation of the FE model is introduced, which enables the use of linear model order reduction. Microresonators are modeled with the introduction of transducer elements, which allow for direct coupling of the electrical and mechanical domain. The coupled system element matrices are linearized around an operating point and reduced. The resulting macromodel is valid for small signal analysis around the bias point, such as harmonic pre-stressed analysis. This is extremely useful for characterizing the frequency response of resonators. Compact modelling of switches preserves the nonlinearity of the device behaviour. Nonlinear reduced order models are obtained by reducing the number of nonlinearities in the system and handling them as input to the system. In this way, the system can be reduced using linear MOR techniques and nonlinearities are introduced directly in the reduced order model. The reduction of the number of system nonlinearities implies the approximation of all distributed forces in the model with lumped forces. Both for microresonators and switches, a procedure for matrices extraction has been developed so that reduced order models include the effects of electrical and mechanical pre-stress. The extraction process is fast and can be done automatically from ANSYS binary files. The method has been applied for the simulation of several devices both at devices and circuit level. Simulation results have been compared with full model simulations, and, when available, experimental data. Reduced order models have proven to conserve the accuracy of finite element method and to give a good description of the overall device behaviour, despite the introduced approximations. In addition, simulation is very fast, both at device and circuit level. A combined process-flow for the integrated fabrication of microresonators and switches has been defined. For this purpose, two processes that are optimized for the independent fabrication of these devices are merged. The major advantage of this process is the possibility to create on-chip circuit blocks that include both microresonators and switches. An application is, for example, aswitched filter bank for wireless transceiver. The process for microresonators fabrication is characterized by the use of silicon on insulator (SOI) wafers and on a deep reactive ion etching (DRIE) step for the creation of the vibrating structures in single-crystal silicon and the use of a sacrificial oxide layer for the definition of resonator to electrode distance. The fabrication of switches is characterized by the use of two different conductive layers for the definition of the actuation electrodes and by the use of a photoresist as a sacrificial layer for the creation of the suspended structure. Both processes have a gold electroplating step, for the creation of the resonators electrodes, transmission lines and suspended structures. The combined process flow is designed such that it conserves the basic properties of the original processes. Neither the performance of the resonators nor the performance of the switches results affected by the simultaneous fabrication. Moreover, common fabrication steps are shared, which allows for cheaper and faster fabrication.

Silicon Photonics Integrated Circuits for Flexible Optical Systems

This dissertation deals with the design and the characterization of novel reconfigurable silicon-on-insulator (SOI) devices to filter and route optical signals on-chip. Design is carried out through circuit simulations based on basic circuit elements (Building Blocks, BBs) in order to prove the feasibility of an approach allowing to move the design of Photonic Integrated Circuits (PICs) toward the system level. CMOS compatibility and large integration scale make SOI one of the most promising material to realize PICs. The concepts of generic foundry and BB based circuit simulations for the design are emerging as a solution to reduce the costs and increase the circuit complexity. To validate the BB based approach, the development of some of the most important BBs is performed first. A novel tunable coupler is also presented and it is demonstrated to be a valuable alternative to the known solutions. Two novel multi-element PICs are then analysed: a narrow linewidth single mode resonator and a passband filter with widely tunable bandwidth. Extensive circuit simulations are carried out to determine their performance, taking into account fabrication tolerances. The first PIC is based on two Grating Assisted Couplers in a ring resonator (RR) configuration. It is shown that a trade-off between performance, resonance bandwidth and device footprint has to be performed. The device could be employed to realize reconfigurable add-drop de/multiplexers. Sensitivity with respect to fabrication tolerances and spurious effects is however observed. The second PIC is based on an unbalanced Mach-Zehnder interferometer loaded with two RRs. Overall good performance and robustness to fabrication tolerances and nonlinear effects have confirmed its applicability for the realization of flexible optical systems. Simulated and measured devices behaviour is shown to be in agreement thus demonstrating the viability of a BB based approach to the design of complex PICs.

Silicon on silicon : self-organized nanotip arrays formed in reactive Ar+H2 plasmas

The formation of arrays of vertically aligned nanotips on a moderately heated (up to 500 degrees C) Si surface exposed to reactive low-temperature radio frequency (RF) Ar+H(2) plasmas is studied. It is demonstrated that the nanotip surface density, aspect ratio and height dispersion strongly depend on the substrate temperature, discharge power, and gas composition. It is shown that nanotips with aspect ratios from 2.0 to 4.0 can only be produced at a higher RF power density (41.7 mW cm(-3)) and a hydrogen content of about 60%, and that larger aspect ratios can be achieved at substrate temperatures of about 300 degrees C. The use of higher (up to 500 degrees C) temperatures leads to a decrease of the aspect ratio but promotes the formation of more uniform arrays with the height dispersion decreasing to 1.5. At lower (approximately 20 mW cm(-3)) RF power density, only semispherical nanodots can be produced. Based on these experimental results, a nanotip formation scenario is proposed suggesting that sputtering, etching, hydrogen termination, and atom/radical re-deposition are the main concurrent mechanisms for the nanostructure formation. Numerical calculations of the ion flux distribution and hydrogen termination profiles can be used to predict the nanotip shapes and are in a good agreement with the experimental results. This approach can be applied to describe the kinetics of low-temperature formation of other nanoscale materials by plasma treatment.

Selective metallization on insulator surfaces with femtosecond laser pulses

We report selective metallization on surfaces of insulators ( glass slides and lithium niobate crystal) based on femtosecond laser modification combined with electroless plating. The process is mainly composed of four steps: (1) formation of silver nitrate thin films on the surfaces of glass or crystal substrates; (2) generation of silver particles in the irradiated area by femtosecond laser direct writing; (3) removal of unirradiated silver nitrate films; and (4) selective electroless plating in the modified area. We discuss the mechanism of selective metallization on the insulators. Moreover, we investigate the electrical and adhesive properties of the copper microstructures patterned on the insulator surfaces, showing great potential of integrating electrical functions into lab-on-a-chip devices. (C) 2007 Optical Society of America.

More oomph

An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

REGROWTH RATES OF AMORPHOUS LAYERS IN SILICON-ON-SAPPHIRE FILMS.

The rate and direction of regrowth of amorphous layers, created by self-implantation, in silicon-on-sapphire (SOS) have been studied using time resolved reflectivity (TRR) experiments performed simultaneously at two wavelengths. Regrowth of an amorphous layer towards the surface was observed in specimens implanted with 3 multiplied by (times) 10**1**5Si** plus /cm**2 at 50keV and regrowth of a buried amorphous layer, from a surface seed towards the sapphire, was observed in specimens implanted with 1 multiplied by (times) 10**1**5Si** plus /cm**2 at 175keV. Rapid isothermal heating to regrow the layers was performed in an electron beam annealing system. The combination of 514. 5nm and 632. 8nm wavelengths was found to be particularly useful for TRR studies since the high absorption in amorphous silicon, at the shorter wavelength, means that the TRR trace is not complicated by reflection from the silicon-sapphire interface until regrowth is nearly complete.

Room-temperature emission at telecom wavelengths from silicon photonic crystal nanocavities

Strongly enhanced light emission at wavelengths between 1.3 and 1.6 μm is reported at room temperature in silicon photonic crystal (PhC) nanocavities with optimized out-coupling efficiency. Sharp peaks corresponding to the resonant modes of PhC nanocavities dominate the broad sub-bandgap emission from optically active defects in the crystalline Si membrane. We measure a 300-fold enhancement of the emission from the PhC nanocavity due to a combination of far-field enhancement and the Purcell effect. The cavity enhanced emission has a very weak temperature dependence, namely less than a factor of 2 reduction between 10 K and room temperature, which makes this approach suitable for the realization of efficient light sources as well as providing a quick and easy tool for the broadband optical characterization of silicon-on-insulator nanostructures. © 2011 American Institute of Physics.