Implementação de um sistema embarcado aplicado ao controle de pressão arterial

Hypertension is a dangerous disease that can cause serious harm to a patient health. In some situations the necessity to control this pressure is even greater, as in surgical procedures and post-surgical patients. To decrease the chances of a complication, it is necessary to reduce blood pressure as soon as possible. Continuous infusion of vasodilators drugs, such as sodium nitroprusside (SNP), rapidly decreased blood pressure in most patients, avoiding major problems. Maintaining the desired blood pressure requires constant monitoring of arterial blood pressure and frequently adjusting the drug infusion rate. Manual control of arterial blood pressure by clinical personnel is very demanding, time consuming and, as a result, sometimes of poor quality. Thus, the aim of this work is the design and implementation of a database of tuned controllers based on patients models, in order to find a suitable PID to be embedded in a Programmable Integrated Circuit (PIC), which has a smaller cost, smaller size and lower power consumption. For best results in controlling the blood pressure and choosing the adequate controller, tuning algorithms, system identification techniques and Smith predictor are used. This work also introduces a monitoring system to assist in detecting anomalies and optimize the process of patient care.

Implementação Hardware/Software da estimação de movimento segundo o padrão H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Avaliação do Uso de Smartphones na Interação com as Aplicações da Televisão Digital Brasileira

Brazil is going through the process from analogical transmission to digital transmission. This new technology, in addition to providing a high quality audio and video, also allows applications to execute on television. Equipment called Set-Top Box are needed to allow the reception of this new signal and create the appropriate environment necessary to execute applications. At first, the only way to interact with these applications is given by remote control. However, the remote control has serious usability problems when used to interact with some types of applications. This research suggests a software resources implementation capable to create a environment that allows a smartphone to interact with applications. Besides this implementation, is performed a comparative study between use remote controle and smartphones to interact with applications of digital television, taking into account parameters related to usability. After analysis of data collected by the comparative study is possible to identify which device provides an interactive experience more interesting for users

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Contribuições para verificação automática de applets javacard

The widespread growth in the use of smart cards (by banks, transport services, and cell phones, etc) has brought an important fact that must be addressed: the need of tools that can be used to verify such cards, so to guarantee the correctness of their software. As the vast majority of cards that are being developed nowadays use the JavaCard technology as they software layer, the use of the Java Modeling Language (JML) to specify their programs appear as a natural solution. JML is a formal language tailored to Java. It has been inspired by methodologies from Larch and Eiffel, and has been widely adopted as the de facto language when dealing with specification of any Java related program. Various tools that make use of JML have already been developed, covering a wide range of functionalities, such as run time and static checking. But the tools existent so far for static checking are not fully automated, and, those that are, do not offer an adequate level of soundness and completeness. Our objective is to contribute to a series of techniques, that can be used to accomplish a fully automated and confident verification of JavaCard applets. In this work we present the first steps to this. With the use of a software platform comprised by Krakatoa, Why and haRVey, we developed a set of techniques to reduce the size of the theory necessary to verify the specifications. Such techniques have yielded very good results, with gains of almost 100% in all tested cases, and has proved as a valuable technique to be used, not only in this, but in most real world problems related to automatic verification

Implementação da técnica de software pipelining na rede em chip IPNoSyS

Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism

Controle adaptativo por modelo de referencia e estrutura variável discreto no tempo

With the technology progess, embedded systems using adaptive techniques are being used frequently. One of these techniques is the Variable Structure Model- Reference Adaptive Control (VS-MRAC). The implementation of this technique in embedded systems, requires consideration of a sampling period which if not taken into consideration, can adversely affect system performance and even takes the system to instability. This work proposes a stability analysis of a discrete-time VS-MRAC accomplished for SISO linear time-invariant plants with relative degree one. The aim is to analyse the in uence of the sampling period in the system performance and the relation of this period with the chattering and system instability

Determination of resonant frequencies of triangular and rectangular microstrip antennas, using artificial neural networks

This paper presents models that can be used in the design of microstrip antennas for mobile communications. The antennas can be triangular or rectangular. The presented models are compared with deterministic and empirical models based on artificial neural networks (ANN) presented in the literature. The models are based on Perceptron Multilayer (PML) and Radial Basis Function (RBF) ANN. RBF based models presented the best results. Also, the models can be embedded in CAD systems, in order to design microstrip antennas for mobile communications.

A general technique to embed non-uniform discontinuities into standard solid finite elements

A general technique to embed non-uniform displacement discontinuities into standard solid finite elements is presented. The technique is based on the decomposition of the kinematic fields into a component related to the deformation of the solid portion of the element and one related to the rigid-body motion due to a displacement discontinuity. This decomposition simplifies the incorporation of discontinuity interfaces and provides a suitable framework to account for non-uniform discontinuity modes. The present publication addresses two families of finite element formulations: displacement-based and stress hybrid finite element. © 2005 Elsevier Ltd. All rights reserved.

Conception of wheeled mobile robots with reconfigurable control using integrate prototyping

With the fast innovation of the hardware and software technologies using rapid prototyping devices, with application in the robotics and automation, more and more it becomes necessary the development of applications based on methodologies that facilitate future modifications, updates and enhancements in the original projected system. This paper presents a conception of mobile robots using rapid prototyping, distributing the several control actions in growing levels of complexity and using resources of reconfigurable computing proposal oriented to embed systems implementation. Software and the hardware are structuralized in independents blocks, with connection through common bus. The study and applications of new structures control that permits good performance in relation to the parameter variations. This kind of controller can be tested on different platform representing the wheeled mobile robots using reprogrammable logic components (FPGA). © 2006 IEEE.

Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

Virtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9 and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). © 2011 IEEE.

Algoritmos de detecção de bordas implementados em FPGA

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Identificação do teor de nitrogênio foliar em cana-de-açúcar no estágio inicial de crescimento utilizando infravermelho próximo e sistemas inteligentes

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Compilação de bytecodes Java para um ambiente de arquitetura reconfigurável

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Sistema embarcado para monitoramento de harpia (Harpia harpyja)

Esta dissertação consiste no projeto e implementação parcial de um sistema integrado de monitoramento da ave Harpia (Harpia harpyja), espécie encontrada na Amazônia, Cerrado e Mata Atlântica. O sistema de monitoramento é estruturado em três etapas: coleta, armazenamento e transmissão de dados. A primeira etapa consiste na coleta de dados a partir de sensores, podendo detectar a presença de pássaros no ninho, também o sistema conta com o auxílio de uma câmera responsável pela captura de vídeo e áudio. A segunda etapa destina-se ao pré-processamento e armazenamento de todas as informações coletadas. A terceira etapa é responsável pela transmissão dos dados através de satélite, utilizando o Sistema Brasileiro de Coleta de Dados Ambientais (SBCDA). Além disso, foi realizado o desenvolvimento de um protótipo utilizado para o monitoramento. Técnicas de sistemas embarcados são expostas para o leitor e o processo de detecção desta espécie é avaliado.