Using multiple abstraction levels to speedup an MPSoC virtual platform simulator
Contribuinte(s) |
Universidade Estadual Paulista (UNESP) |
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Data(s) |
27/05/2014
27/05/2014
28/07/2011
|
Resumo |
Virtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9 and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). © 2011 IEEE. |
Formato |
99-105 |
Identificador |
http://dx.doi.org/10.1109/RSP.2011.5929982 Proceedings of the International Workshop on Rapid System Prototyping, p. 99-105. 1074-6005 http://hdl.handle.net/11449/72565 10.1109/RSP.2011.5929982 2-s2.0-79960688876 |
Idioma(s) |
eng |
Relação |
Proceedings of the International Workshop on Rapid System Prototyping |
Direitos |
closedAccess |
Palavras-Chave | #Abstraction level #Communication mechanisms #Cycle accurate #Design space exploration #Fast simulation #Hybrid platform #Instruction set simulators #Power estimations #Simulation platform #Standard deviation #Virtual platform #Embedded systems #Multiprocessing systems #Software design #Space platforms #Space research #Specifications #Verification #Computer software |
Tipo |
info:eu-repo/semantics/conferencePaper |