820 resultados para Delay discounting
Resumo:
The turn-on delay time jitter of four different unbiased gain-switched laser types is determined by measuring the temporal probability distribution of the leading edge of the emitted optical pulse. One single-mode 1.5-mu-m distributed feed-back laser and three multimode Fabry-Perot lasers emitting at 750 nm and 1.3-mu-m are investigated. The jitter is found to decrease for all lasers with increasing injection current. For multimode lasers it decreases from 8 ps excited slightly above threshold down to below 2 ps at three times the threshold current. The jitter of the distributed feedback (DFB) laser is a factor of 3-5 larger than the jitter of the three multimode lasers. A new model to predict the turn-on delay time jitter is presented and explains the experiments quantitatively.
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Multi-hit 3-layer delay-line anode (Hexanode) has an increased ability to detect multi-hit events in a collision experiment. Coupled with a pair of micro-channel plates, it can provide position information of the particles even if the particles arrive at the same time or within small time dwell. But it suffers from some ambiguous outputs and signal losses due to timing order and triggering thresholds etc. We have developed a signal reconstruction program to correct those events. After the program correction, the dead time only exists when 2 paxticles arrive at the same time and the same position within a much smaller range. With the combination of Hexanode and the program, the experimental efficiencies will be greatly improved in near threshold double ionization on He collisions.
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气体探测器有成本低廉、制备简单、性能可靠和方便使用等特点。研制了一种5层板结构的延迟线平行板雪崩电离室(PPAC),用于兰州放射性束流线(RIBLL)上开展的实验。在57.6MeV/u的6He束流条件下测试了这种探测器对高能轻粒子的适用性,得到了位置分辨为1.8mm(FWHM),时间分辨为2.6ns,以及可靠的探测效率。
Resumo:
For a sphere electrode enclosed in finite-volume electrolyte, the measured current will deviate from the result predicted by the semi-infinite diffusion theory after some time. By random-walk simulation, we compared this time to the one needed for diffusion layer to reach electrolyte boundary, and revealed a clear signal delay of electrochemical current. Further we presented a quantitative description of this delay time. The simulation results suggested that the semi-infinite diffusion theory can even be applied when the theoretical diffusion layer grows to 1.28 electrolyte thicknesses, with an accuracy better than 0.5%. We attributed this time delay to the molecules' finite propagation velocity. Finally, we discussed how this delay can influence and facilitate the following electrochemical detection towards the nanometer and single-cell scale.
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For some species, hereditary factors have great effects on their population evolution, which can be described by the well-known Volterra model. A model developed is investigated in this article, considering the seasonal variation of the environment, where the diffusive effect of the population is also considered. The main approaches employed here are the upper-lower solution method and the monotone iteration technique. The results show that whether the species dies out or not depends on the relations among the birth rate, the death rate, the competition rate, the diffusivity and the hereditary effects. The evolution of the population may show asymptotic periodicity, provided a certain condition is satisfied for the above factors. (c) 2006 Elsevier Ltd. All rights reserved.
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The main aim of this paper is to investigate the effects of the impulse and time delay on a type of parabolic equations. In view of the characteristics of the equation, a particular iteration scheme is adopted. The results show that Under certain conditions on the coefficients of the equation and the impulse, the solution oscillates in a particular manner-called "asymptotic weighted-periodicity".
Resumo:
In this paper, a Lyapunov function candidate is introduced for multivariable systems with inner delays, without assuming a priori stability for the nondelayed subsystem. By using this Lyapunov function, a controller is deduced. Such a controller utilizes an input-output description of the original system, a circumstance that facilitates practical applications of the proposed approach.
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A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state How diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated.
Resumo:
With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.
Resumo:
Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations. © 2010 IEEE.
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Pigeons and other animals soon learn to wait (pause) after food delivery on periodic-food schedules before resuming the food-rewarded response. Under most conditions the steady-state duration of the average waiting time, t, is a linear function of the typical interfood interval. We describe three experiments designed to explore the limits of this process. In all experiments, t was associated with one key color and the subsequent food delay, T, with another. In the first experiment, we compared the relation between t (waiting time) and T (food delay) under two conditions: when T was held constant, and when T was an inverse function of t. The pigeons could maximize the rate of food delivery under the first condition by setting t to a consistently short value; optimal behavior under the second condition required a linear relation with unit slope between t and T. Despite this difference in optimal policy, the pigeons in both cases showed the same linear relation, with slope less than one, between t and T. This result was confirmed in a second parametric experiment that added a third condition, in which T + t was held constant. Linear waiting appears to be an obligatory rule for pigeons. In a third experiment we arranged for a multiplicative relation between t and T (positive feedback), and produced either very short or very long waiting times as predicted by a quasi-dynamic model in which waiting time is strongly determined by the just-preceding food delay.