Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

JPEG encoder system-on-a-chip demonstrator

The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.