A functional specification and validation model for networks on chip in the ACL2 logic


Autoria(s): Schmaltz, J.; Borrione, D.
Contribuinte(s)

Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF) - Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP) - Institut National Polytechnique de Grenoble (INPG) - Centre National de la Recherche Scientifique (CNRS) - Université Grenoble Alpes (UGA)

Cobertura

Austin, Texas, United States

Data(s)

18/11/2004

Resumo

International audience

We present a functional model used to specify and validate, in the ACL2 logic, a system on a chip communication architecture named Octagon. The functional model is briey introduced before being developed on the case study. We define and validate the routing algorithm, a simple scheduling algorithm and the correctness of read and write operations which includes the proof that messages travel over the network without being modified and eventually reach their expected destination.

Identificador

hal-01392593

https://hal.archives-ouvertes.fr/hal-01392593

Idioma(s)

fr

Publicador

HAL CCSD

Direitos

http://creativecommons.org/licenses/by-nc/

Fonte

5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04)

https://hal.archives-ouvertes.fr/hal-01392593

5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04), Nov 2004, Austin, Texas, États-Unis. pp.1-18, Proceedings

Palavras-Chave #PACS 8542 #[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Tipo

info:eu-repo/semantics/conferenceObject

Conference papers