Abeta oligomer toxicity inhibitor protects memory in models of synaptic toxicity

BACKGROUND AND PURPOSE:

Amyloid-ß (Aß) aggregation into synaptotoxic, prefibrillar oligomers is a major pathogenic event underlying the neuropathology of Alzheimer's disease (AD). The pharmacological and neuroprotective properties of a novel Aß aggregation inhibitor, SEN1269, were investigated on aggregation and cell viability and in test systems relevant to synaptic function and memory, using both synthetic Aß(1-42) and cell-derived Aß oligomers.
EXPERIMENTAL APPROACH:

Surface plasmon resonance studies measured binding of SEN1269 to Aß(1-42) . Thioflavin-T fluorescence and MTT assays were used to measure its ability to block Aß(1-42) -induced aggregation and reduction in cell viability. In vitro and in vivo long-term potentiation (LTP) experiments measured the effect of SEN1269 on deficits induced by synthetic Aß(1-42) and cell-derived Aß oligomers. Following i.c.v. administration of the latter, a complex (alternating-lever cyclic ratio) schedule of operant responding measured effects on memory in freely moving rats.
KEY RESULTS:

SEN1269 demonstrated direct binding to monomeric Aß(1-42) , produced a concentration-related blockade of Aß(1-42) aggregation and protected neuronal cell lines exposed to Aß(1-42) . In vitro, SEN1269 alleviated deficits in hippocampal LTP induced by Aß(1-42) and cell-derived Aß oligomers. In vivo, SEN1269 reduced the deficits in LTP and memory induced by i.c.v. administration of cell-derived Aß oligomers.
CONCLUSIONS AND IMPLICATIONS:

SEN1269 protected cells exposed to Aß(1-42) , displayed central activity with respect to reducing Aß-induced neurotoxicity and was neuroprotective in electrophysiological and behavioural models of memory relevant to Aß-induced neurodegeneration. It represents a promising lead for designing inhibitors of Aß-mediated synaptic toxicity as potential neuroprotective agents for treating AD.

Feedforward Control of Shape Memory Alloy Actuators Using Fuzzy-Based Inverse Preisach Model

This brief investigates a possible application of the inverse Preisach model in combination with the feedforward and feedback control strategies to control shape memory alloy actuators. In the feedforward control design, a fuzzy-based inverse Preisach model is used to compensate for the hysteresis nonlinearity effect. An extrema input history and a fuzzy inference is utilized to replace the inverse classical Preisach model. This work allows for a reduction in the number of experimental parameters and computation time for the inversion of the classical Preisach model. A proportional-integral-derivative (PID) controller is used as a feedback controller to regulate the error between the desired output and the system output. To demonstrate the effectiveness of the proposed controller, real-time control experiment results are presented.

Optimal proportional-integral-derivative control of shape memory alloy actuators using genetic algorithm and the Preisach model

Shape memory alloy (SMA) actuators, which have the ability to return to a predetermined shape when heated, have many potential applications in aeronautics, surgical tools, robotics, and so on. Although the number of applications is increasing, there has been limited success in precise motion control owing to the hysteresis effect of these smart actuators. The present paper proposes an optimization of the proportional-integral-derivative (PID) control method for SMA actuators by using genetic algorithm and the Preisach hysteresis model.

Position control of shape memory alloy actuators using self tuning fuzzy PID controller

Shape Memory Alloy (SMA) actuators, which have the ability to return to a predetermined shape when heated, have many potential applications such as aeronautics, surgical tools, robotics and so on. Although the conventional PID controller can be used with slow response systems, there has been limited success in precise motion control of SMA actuators, since the systems are disturbed by unknown factors beside their inherent nonlinear hysteresis and changes in the surrounding environment of the systems. This paper presents a new development of a SMA position control system by using a self-tuning fuzzy PID controller. This control algorithm is used by tuning the parameters of the PID controller thereby integrating fuzzy inference and producing a fuzzy adaptive PID controller, which can then be used to improve the control performance of nonlinear systems. The experimental results of position control of SMA actuators using conventional and self-tuning fuzzy PID controllers are both included in this paper.

Valved Dataflow For FPGA Memory Hierarchy Synthesis

For modern FPGA, implementation of memory intensive processing applications such as high end image and video processing systems necessitates manual design of complex multilevel memory hierarchies incorporating off-chip DDR and onchip BRAM and LUT RAM. In fact, automated synthesis of multi-level memory hierarchies is an open problem facing high level synthesis technologies for FPGA devices. In this paper we describe the first automated solution to this problem.
By exploiting a novel dataflow application modelling dialect, known as Valved Dataflow, we show for the first time how, not only can such architectures be automatically derived, but also that the resulting implementations support real-time processing for current image processing application standards such as H.264. We demonstrate the viability of this approach by reporting the performance and cost of hierarchies automatically generated for Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications on Virtex-5 FPGA.

Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Realising high performance image and signal processing
applications on modern FPGA presents a challenging implementation problem due to the large data frames streaming through these systems. Specifically, to meet the high bandwidth and data storage demands of these applications, complex hierarchical memory architectures must be manually specified
at the Register Transfer Level (RTL). Automated approaches which convert high-level operation descriptions, for instance in the form of C programs, to an FPGA architecture, are unable to automatically realise such architectures. This paper
presents a solution to this problem. It presents a compiler to automatically derive such memory architectures from a C program. By transforming the input C program to a unique dataflow modelling dialect, known as Valved Dataflow (VDF), a mapping and synthesis approach developed for this dialect can
be exploited to automatically create high performance image and video processing architectures. Memory intensive C kernels for Motion Estimation (CIF Frames at 30 fps), Matrix Multiplication (128x128 @ 500 iter/sec) and Sobel Edge Detection (720p @ 30 fps), which are unrealisable by current state-of-the-art C-based synthesis tools, are automatically derived from a C description of the algorithm.

Reduced-memory multirate vector quantisation

A new method is proposed which reduces the size of the memory needed to implement multirate vector quantizers. Investigations have shown that the performance of the coders implemented using this approach is comparable to that obtained from standard systems. The proposed method can therefore be used to reduce the hardware required to implement real-time speech coders.

Living is Information Processing: From Molecules to Global Systems

We extend the concept that life is an informational phenomenon, at every level of organisation, from molecules to the global ecological system. According to this thesis: (a) living is information processing, in which memory is maintained by both molecular states and ecological states as well as the more obvious nucleic acid coding; (b) this information processing has one overall function-to perpetuate itself; and (c) the processing method is filtration (cognition) of, and synthesis of, information at lower levels to appear at higher levels in complex systems (emergence). We show how information patterns, are united by the creation of mutual context, generating persistent consequences, to result in 'functional information'. This constructive process forms arbitrarily large complexes of information, the combined effects of which include the functions of life. Molecules and simple organisms have already been measured in terms of functional information content; we show how quantification may be extended to each level of organisation up to the ecological. In terms of a computer analogy, life is both the data and the program and its biochemical structure is the way the information is embodied. This idea supports the seamless integration of life at all scales with the physical universe. The innovation reported here is essentially to integrate these ideas, basing information on the 'general definition' of information, rather than simply the statistics of information, thereby explaining how functional information operates throughout life. © 2013 Springer Science+Business Media Dordrecht.

Targeting distributed systems in FastFlow

FastFlow is a structured parallel programming framework targeting shared memory multi-core architectures. In this paper we introduce a FastFlow extension aimed at supporting also a network of multi-core workstations. The extension supports the execution of FastFlow programs by coordinating-in a structured way-the fine grain parallel activities running on a single workstation. We discuss the design and the implementation of this extension presenting preliminary experimental results validating it on state-of-the-art networked multi-core nodes. © 2013 Springer-Verlag.

Generalized Langevin equation: An efficient approach to nonequilibrium molecular dynamics of open systems

The generalized Langevin equation (GLE) has been recently suggested to simulate the time evolution of classical solid and molecular systems when considering general nonequilibrium processes. In this approach, a part of the whole system (an open system), which interacts and exchanges energy with its dissipative environment, is studied. Because the GLE is derived by projecting out exactly the harmonic environment, the coupling to it is realistic, while the equations of motion are non-Markovian. Although the GLE formalism has already found promising applications, e. g., in nanotribology and as a powerful thermostat for equilibration in classical molecular dynamics simulations, efficient algorithms to solve the GLE for realistic memory kernels are highly nontrivial, especially if the memory kernels decay nonexponentially. This is due to the fact that one has to generate a colored noise and take account of the memory effects in a consistent manner. In this paper, we present a simple, yet efficient, algorithm for solving the GLE for practical memory kernels and we demonstrate its capability for the exactly solvable case of a harmonic oscillator coupled to a Debye bath.

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory
access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement
the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to
67.1%, under a power cap.

An optimized stereo vision implementation for embedded systems: application to RGB and Infra-Red images

The aim of this paper is to demonstrate the applicability and the effectiveness of a computationally demanding stereo matching algorithm in different lowcost and low-complexity embedded devices, by focusing on the analysis of timing and image quality performances. Various optimizations have been implemented to allow its deployment on specific hardware architectures while decreasing memory and processing time requirements: (1) reduction of color channel information and resolution for input images, (2) low-level software optimizations such as parallel computation, replacement of function calls or loop unrolling, (3) reduction of redundant data structures and internal data representation. The feasibility of a stereovision system on a low cost platform is evaluated by using standard datasets and images taken from Infra-Red (IR) cameras. Analysis of the resulting disparity map accuracy with respect to a full-size dataset is performed as well as the testing of suboptimal solutions

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.