Optimal association of mobile wireless devices with a WLAN-3G access network

In this paper, we consider the problem of association of wireless stations (STAs) with an access network served by a wireless local area network (WLAN) and a 3G cellular network. There is a set of WLAN Access Points (APs) and a set of 3G Base Stations (BSs) and a number of STAs each of which needs to be associated with one of the APs or one of the BSs. We concentrate on downlink bulk elastic transfers. Each association provides each ST with a certain transfer rate. We evaluate an association on the basis of the sum log utility of the transfer rates and seek the utility maximizing association. We also obtain the optimal time scheduling of service from a 3G BS to the associated STAs. We propose a fast iterative heuristic algorithm to compute an association. Numerical results show that our algorithm converges in a few steps yielding an association that is within 1% (in objective value) of the optimal (obtained through exhaustive search); in most cases the algorithm yields an optimal solution.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.

Multilevel inverters for low-power application

Multilevel inverters are an attractive solution in the medium-voltage and high-power applications. However in the low-power range also it can be a better solution compared to two-level inverters, if MOSFETs are used as devices switching in the order of 100 kHz. The effect of clamping diodes in the diode-clamped multilevel inverters play an important role in determining its efficiency. Power loss introduced by the reverse recovery of MOSFET body diode prohibits the use of MOSFET in hard-switched inverter legs. A technique of avoiding reverse recovery loss of MOSFET body diode in a three-level neutral point clamped inverter is suggested. The use of multilevel inverters topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps in reducing the size of the inverter. This study elaborates the trade-off analysis to quantify the suitability of multilevel inverters in the low-power applications. Advantages of using a MOSFET-based three-level diode-clamped inverter for a PM motor drive and UPS systems are discussed.

Editorial optical computing circuits, devices and systems

Information forms the basis of modern technology. To meet the ever-increasing demand for information, means have to be devised for a more efficient and better-equipped technology to intelligibly process data. Advances in photonics have made their impact on each of the four key applications in information processing, i.e., acquisition, transmission, storage and processing of information. The inherent advantages of ultrahigh bandwidth, high speed and low-loss transmission has already established fiber-optics as the backbone of communication technology. However, the optics to electronics inter-conversion at the transmitter and receiver ends severely limits both the speed and bit rate of lightwave communication systems. As the trend towards still faster and higher capacity systems continues, it has become increasingly necessary to perform more and more signal-processing operations in the optical domain itself, i.e., with all-optical components and devices that possess a high bandwidth and can perform parallel processing functions to eliminate the electronic bottleneck.

Polymer blend based photovoltaic devices.

Solar cells on thin conformable substrates require conventional plastics such asPS and PMMA that provide better mechanical and environmental stability with cost reduction. We can also tune charge transfer between PPV derivatives and fullerene derivatives via morphology control of the plastics in the solar cells. Our group has conducted morphology evolution studies in nano- and microscale light emitting domains in poly (2-methoxy, 5-(2'-ethyl-hexyloxy)-p-phenylenevinylene) (MEH-PPV) and poly (methyl methacrylate) (PMMA) blends. Our current research has been focused on tricomponent-photoactive solar cells which comprise MEH-PPV, PMMA, and [6,6]-phenyl C61-butyric acid methyl ester (PCBM, Figure 1) in the photoactive layer. Morphology control of the photoactive materials and fine tuning of photovoltaic properties for the solar cells are our primary interest. Similar work has been done by the Sariciftci research group. Additionally, a study on inter- and intramolecular photoinduced charge transfer using MEH-PPV derivatives that have different conjugation lengths (Figure 1, n=1 and 0.85) has been performed.

Effect of scaling on the non-quasi-static behaviour of the MOSFET for RF ICs

The effect of scaling (1 μm to 0.09 μm) on the non-quasi-static (NQS) behaviour of the MOSFET has been studied using process and device simulation. It is shown that under fixed gate (Vgs) and drain (Vds) bias voltages, the NQS transition frequency (fNQS) scales as 1/Leff rather than 1/L2eff due to the velocity saturation effect. However, under the practical scaling guidelines, considering the scaling of supply voltage as well, fNQS shows a turn around effect at the sub 100 nm regime. The relation between unity gain frequency (ft) and fNQS is also evaluated and it is shown that ft and fNQS have similar trends with scaling.

Reactive power optimization with different objectives in large power systems including HVDC systems and FACTS devices

Present day power systems are growing in size and complexity of operation with inter connections to neighboring systems, introduction of large generating units, EHV 400/765 kV AC transmission systems, HVDC systems and more sophisticated control devices such as FACTS. For planning and operational studies, it requires suitable modeling of all components in the power system, as the number of HVDC systems and FACTS devices of different type are incorporated in the system. This paper presents reactive power optimization with three objectives to minimize the sum of the squares of the voltage deviations (ve) of the load buses, minimization of sum of squares of voltage stability L-indices of load buses (¿L2), and also the system real power loss (Ploss) minimization. The proposed methods have been tested on typical sample system. Results for Indian 96-bus equivalent system including HVDC terminal and UPFC under normal and contingency conditions are presented.

Electrical breakdown of carbon nanotube devices and the predictability of breakdown position

We have investigated electrical transport properties of long (>10 mu m) multiwalled carbon nanotubes (NTs) by dividing individuals into several segments of identical length. Each segment has different resistance because of the random distribution of defect density in an NT and is corroborated by Raman studies. Higher is the resistance, lower is the current required to break the segments indicating that breakdown occurs at the highly resistive segment/site and not necessarily at the middle. This is consistent with the one-dimensional thermal transport model. We have demonstrated the healing of defects by annealing at moderate temperatures or by current annealing. To strengthen our mechanism, we have carried out electrical breakdown of nitrogen doped NTs (NNTs) with diameter variation from one end to the other. It reveals that the electrical breakdown occurs selectively at the narrower diameter region. Overall, we believe that our results will help to predict the breakdown position of both semiconducting and metallic NTs. Copyright 2012 Author(s). This article is distributed under a Creative Commons Attribution 3.0 Unported License. http://dx.doi.org/10.1063/1.4720426]

Substrate temperature influenced physical properties of silicon MOS devices with TiO2 gate dielectric

DC reactive magnetron sputtering technique was employed for deposition of titanium dioxide (TiO2) films. The films were formed on Corning glass and p-Si (100) substrates by sputtering of titanium target in an oxygen partial pressure of 6x10-2 Pa and at different substrate temperatures in the range 303 673 K. The films formed at 303 K were X-ray amorphous whereas those deposited at substrate temperatures?=?473 K were transformed into polycrystalline nature with anatase phase of TiO2. Fourier transform infrared spectroscopic studies confirmed the presence of characteristic bonding configuration of TiO2. The surface morphology of the films was significantly influenced by the substrate temperature. MOS capacitor with Al/TiO2/p-Si sandwich structure was fabricated and performed currentvoltage and capacitancevoltage characteristics. At an applied gate voltage of 1.5 V, the leakage current density of the device decreased from 1.8?x?10-6 to 5.4?x?10-8 A/cm2 with the increase of substrate temperature from 303 to 673 K. The electrical conduction in the MOS structure was more predominant with Schottky emission and Fowler-Nordheim conduction. The dielectric constant (at 1 MHz) of the films increased from 6 to 20 with increase of substrate temperature. The optical band gap of the films increased from 3.50 to 3.56 eV and refractive index from 2.20 to 2.37 with the increase of substrate temperature from 303 to 673 K. Copyright (c) 2012 John Wiley & Sons, Ltd.

Graphene transistors for CMOS applications: opportunities and challenges

In the last decade, there has been a tremendous interest in Graphene transistors. The greatest advantage for CMOS nanoelectronics applications is the fact that Graphene is compatible with planar CMOS technology and potentially offers excellent short channel properties. Because of the zero bandgap, it will not be possible to turn off the MOSFET efficiently and hence the typical on current to off current ratio (Ion/Ioff) has been less than 10. Several techniques have been proposed to open the bandgap in Graphene. It has been demonstrated, both theoretically and experimentally, that Graphene Nanoribbons (GNR) show a bandgap which is inversely proportional to their width. GNRs with about 20 nm width have bandgaps in the range of 100meV. But it is very difficult to obtain GNRs with well defined edges. An alternate technique to open the band gap is to use bilayer Graphene (BLG), with an asymmetric bias applied in the direction perpendicular to their plane. Another important CMOS metric, the subthreshold slope is also limited by the inability to turn off the transistor. However, these devices could be attractive for RF CMOS applications. But even for analog and RF applications the non-saturating behavior of the drain current can be an issue. Although some studies have reported current saturation, the mechanisms are still not very clear. In this talk we present some of our recent findings, based on simulations and experiments, and propose possible solutions to obtain high on current to off current ratio. A detailed study on high field transport in grapheme transistors, relevant for analog and RF applications will also be presented.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Analysing modifica-tions in the synthesis of multiple state mechanical devices using configuration space and topology graphs

Automated synthesis of mechanical designs is an important step towards the development of an intelligent CAD system. Research into methods for supporting conceptual design using automated synthesis has attracted much attention in the past decades. In our research, ten experimental studies are conducted to find out how designers synthesize solution concepts for multi-state mechanical devices. The designers are asked to think aloud, while carrying out the synthesis. These design synthesis processes are video recorded. It has been found that modification of kinematic pairs and mechanisms is the major activity carried out by all the designers. This paper presents an analysis of these synthesis processes using configuration space and topology graph to identify and classify the types of modifications that take place. Understanding of these modification processes and the context in which they happened is crucial to develop a system for supporting design synthesis of multiple state mechanical devices that is capable of creating a comprehensive variety of solution alternatives.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.