Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo

BRITTO, Ricardo S.; MEDEIROS, Adelardo A. D.; ALSINA, Pablo J. Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo. In: SIMPÓSIO BRASILEIRO DE AUTOMAÇÃO INTELIGENTE,8., 2007, Florianópolis. Anais... Florianópolis: SBAI, 2007.

Accelerated ageing test to evaluate seed vigor in pumpkin and zucchini seeds

The accelerated ageing (AA) test is widely used to evaluate seed vigor in various species including vegetable crops. The objective of this work was to study procedures for conducting AA to evaluate seed vigor of pumpkin and zucchini seed lots. Five seed lots of commercially acceptable quality (germination) standards were selected from both cv. `Menina Brasileira' (zucchini) and `Barbara' Hybrid (pumpkin). The following tests were conducted: standard germination, the first count of germination, and AA with and without saline solution (periods of 48, 72 and 96 hours). For each combination of temperature and ageing period, seeds were placed in a single layer on a screen in a germination plastic box with either 40 mL deionized water or 40g NaCl/100mL of water. Both AA methods identified lots 2 and 5 of `Menina Brasileira' and lot 10 of `Barbara' hybrid as having the lowest physiological quality. The temperature 41 C promoted a more drastic reduction in germination than did 38 C. This observation was more marked after 96 hours. Based on the results obtained, it can be concluded that the combination 41 degrees C/96 hours should be used to evaluate the physiological potential of pumpkin and zucchini seeds; however, additional studies are necessary to evaluate other combinations and confirm this indication.

Accelerated ageing and controlled deterioration in beetroot seeds

It is fundamentally important that adequate tests are used to evaluate the physiological quality of produced and commercialized seeds. The objective of this work was to study accelerated ageing and controlled deterioration to evaluate seed vigour in beetroot, seeking to associate these results with seedling emergence in the field. Consequently, five seed lots of Top Tall Early Wonder cultivar were submitted to the tests of germination, seedling emergence in the field, accelerated ageing (using periods of 24, 48 and 72 hours at 42 degrees C) and controlled deterioration (seeds with moisture contents of 22, 24 and 26% at 41 degrees C and 45 degrees C for 12, 24 and 36 hours). Combinations of 72h at 42 degrees C for the accelerated ageing test and 45 degrees C with 24% moisture content for 24h for the controlled deterioration test were sensitive enough to evaluate the physiological potential of beetroot seeds, providing information that was compatible with results of the seedling emergence in the field.

Accelerated aging and seedling field emergence in soybean

Informações sobre a relação entre resultados de testes de vigor conduzidos em laboratório e da emergência de plântulas em campo são fundamentais para a tomada de decisões pelos produtores de sementes. O presente trabalho teve por objetivo verificar a associação entre os resultados do teste de envelhecimento acelerado e a emergência de plântulas de soja [Glycine max (L.) Merrill] em campo, em diferentes safras agrícolas e épocas de semeadura. Assim, foram efetuadas as seguintes avaliações: determinação do grau de umidade das sementes; testes de germinação, de envelhecimento acelerado e de condutividade elétrica, bem como emergência de plântulas em campo. A estimativa mais precisa do desempenho das plântulas em campo foi verificada numa faixa de valores de envelhecimento acelerado > 90%, estimando emergência em campo superior a 80% (r² = 0,90). O teste de envelhecimento acelerado permitiu avaliar a emergência de plântulas de soja em campo. No entanto, à medida que as condições ambientais do local de semeadura foram desviando-se das mais adequadas, a eficiência decresceu.

Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo

In this work, we present a hardware-software architecture for controlling the autonomous mobile robot Kapeck. The hardware of the robot is composed of a set of sensors and actuators organized in a CAN bus. Two embedded computers and eigth microcontroller based boards are used in the system. One of the computers hosts the vision system, due to the significant processing needs of this kind of system. The other computer is used to coordinate and access the CAN bus and to accomplish the other activities of the robot. The microcontroller-based boards are used with the sensors and actuators. The robot has this distributed configuration in order to exhibit a good real-time behavior, where the response time and the temporal predictability of the system is important. We adopted the hybrid deliberative-reactive paradigm in the proposed architecture to conciliate the reactive behavior of the sensors-actuators net and the deliberative activities required to accomplish more complex tasks

Metodologia para adaptação de microarquiteturas microprogramadas soft-core à uma ISA padrão: estudo do impacto sobre a complexidade de hardware para o padrão MIPS

In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments

Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável

Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation.

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Acelerando algoritmos de baixo nível em visão robótica com hardware reconfigurável

A challenge that remains in the robotics field is how to make a robot to react in real time to visual stimulus. Traditional computer vision algorithms used to overcome this problem are still very expensive taking too long when using common computer processors. Very simple algorithms like image filtering or even mathematical morphology operations may take too long. Researchers have implemented image processing algorithms in high parallelism hardware devices in order to cut down the time spent in the algorithms processing, with good results. By using hardware implemented image processing techniques and a platform oriented system that uses the Nios II Processor we propose an approach that uses the hardware processing and event based programming to simplify the vision based systems while at the same time accelerating some parts of the used algorithms

Selection of fungi for accelerated decay in stumps of Eucalyptus spp.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Comparison of non-Ohmic accelerated ageing of the ZnO- and SnO2-based voltage dependent resistors

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Mechanical properties of HIPS/sugarcane bagasse fiber composites after accelerated weathering

The effect of accelerated weathering on the visual appearance and on mechanical properties of high impact polystyrene (HIPS) as well as HIPS reinforced with mercerized and bleached sugarcane bagasse fibers composites are investigated. After accelerated weathering period of 900 h, under UV-B radiation and moisture regular cycles, changes in mechanical properties are investigated by tensile tests. Materials fracture surfaces are investigated by scanning electron microscopy (SEM). The study showed that the exposure time was sufficient to change the visual appearance of HIPS as the composites. From this study, it was observed that composites reinforced with bleached fibers are less susceptible to accelerated weathering exposure than composites reinforced with mercerized fibers, which is explained by the higher amount of lignin present in mercerized fibers. (C) 2010 Published by Elsevier Ltd. Selection and peer-review under responsibility of [name organizer]

Hardware implementation of an analog neural nonderivative optimizer

Analog neural systems that can automatically find the minimum value of the outputs of unknown analog systems, described by convex functions, are studied. When information about derivative or gradient are not used, these systems are called analog nonderivative optimizers. An electronic circuit for the analog neural nonderivative optimizer proposed by Teixeira and Zak, and its simulation with software PSPICE, is presented. With the simulation results and hardware implementation of the system, the validity of the proposed optimizer can be verified. These results are original, from the best of the authors knowledge.

Implementação Hardware/Software da estimação de movimento segundo o padrão H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Geração automática de hardware apartir de especificações formais: estendendo uma abordagem de tradução

A remoção de inconsistências em um projeto é menos custosa quando realizadas nas etapas iniciais da sua concepção. A utilização de Métodos Formais melhora a compreensão dos sistemas além de possuir diversas técnicas, como a especificação e verificação formal, para identificar essas inconsistências nas etapas iniciais de um projeto. Porém, a transformação de uma especificação formal para uma linguagem de programação é uma tarefa não trivial. Quando feita manualmente, é uma tarefa passível da inserção de erros. O uso de ferramentas que auxiliem esta etapa pode proporcionar grandes benefícios ao produto final a ser desenvolvido. Este trabalho propõe a extensão de uma ferramenta cujo foco é a tradução automática de especificações em CSPm para Handel-C. CSP é uma linguagem de descrição formal adequada para trabalhar com sistemas concorrentes. Handel-C é uma linguagem de programação cujo resultado pode ser compilado diretamente para FPGA's. A extensão consiste no aumento no número de operadores CSPm aceitos pela ferramenta, permitindo ao usuário definir processos locais, renomear canais e utilizar guarda booleana em escolhas externas. Além disto, propomos também a implementação de um protocolo de comunicação que elimina algumas restrições da composição paralela de processos na tradução para Handel-C, permitindo que a comunicação entre múltiplos processos possa ser mapeada de maneira consistente e que a mesma somente ocorra quando for autorizada.