Growth regime map for liquid-bound granules: further development and experimental validation

An attempt was made to quantify the boundaries and validate the granule growth regime map for liquid-bound granules recently proposed by Iveson and Litster (AlChE J. 44 (1998) 1510). This regime map postulates that the type of granule growth behaviour is a function of only two dimensionless groups: the amount of granule deformation during collision (characterised by a Stokes deformation number, St(def)) and the maximum granule pore saturation, s(max). The results of experiments performed with a range of materials (glass ballotini, iron ore fines, copper chalcopyrite powder and a sodium sulphate and cellulose mixture) using both drum and high shear mixer granulators were examined. The drum granulation results gave good agreement with the proposed regime map. The boundary between crumb and steady growth occurs at St(def) of order 0.1 and the boundary between steady and induction growth occurs at St(def) of order 0.001. The nucleation only boundary occurs at pore saturations that increase from 70% to 80% with decreasing St(def). However, the high shear mixer results all had St(def) numbers which were too large. This is most likely to be because the chopper tip-speed is an over-estimate of the average impact velocity granules experience and possibly also due to the dynamic yield strength of the materials being significantly greater than the yield strengths measured at low strain rates. Hence, the map is only a useful tool for comparing the granulation behaviour of different materials in the same device. Until we have a better understanding of the flow patterns and impact velocities in granulators, it cannot be used to compare different types of equipment. Theoretical considerations also revealed that several of the regime boundaries are also functions of additional parameters not explicitly contained on the map, such as binder viscosity. (C) 2001 Elsevier Science B.V. All rights reserved.

Nucleation, growth and breakage phenomena in agitated wet granulation processes: a review

Wet agglomeration processes have traditionally been considered an empirical art, with great difficulties in predicting and explaining observed behaviour. Industry has faced a range of problems including large recycle ratios, poor product quality control, surging and even the total failure of scale up from laboratory to full scale production. However, in recent years there has been a rapid advancement in our understanding of the fundamental processes that control granulation behaviour and product properties. This review critically evaluates the current understanding of the three key areas of wet granulation processes: wetting and nucleation, consolidation and growth, and breakage and attrition. Particular emphasis is placed on the fact that there now exist theoretical models which predict or explain the majority of experimentally observed behaviour. Provided that the correct material properties and operating parameters are known, it is now possible to make useful predictions about how a material will granulate. The challenge that now faces us is to transfer these theoretical developments into industrial practice. Standard, reliable methods need to be developed to measure the formulation properties that control granulation behaviour, such as contact angle and dynamic yield strength. There also needs to be a better understanding of the flow patterns, mixing behaviour and impact velocities in different types of granulation equipment. (C) 2001 Elsevier Science B.V. All rights reserved.

Practical and economic advantages of choice feeding systems for laying poultry

Poultry can be managed under different feeding systems, depending on the husbandry skills and the feed available. These systems include the following: (1) a complete dry feed offered as a mash ad libitum; (2) the same feed offered as pellets or crumbles ad libitum; (3) a complete feed with added whole grain; (4) a complete wet feed given once or twice a day; (5) a complete feed offered on a restricted basis; (6) choice feeding. Of all these, an interesting alternative to offering complete diets is choice feeding which can be applied on both a small or large commercial scale. Under choice feeding or free-choice feeding birds are usually offered a choice between three types of feedstuffs: (a) an energy source (e.g. maize, rice bran, sorghum or wheat); (b) a protein source (e.g. soyabean meal, meat meal, fish meal or coconut meal) plus vitamins and minerals and (c), in the case of laying hens, calcium in granular form (i.e. oyster-shell grit). This system differs from the modern commercial practice of offering a complete diet comprising energy and protein sources, ground and mixed together. Under the complete diet system, birds are mainly only able to exercise their appetite for energy. When the environmental temperature varies, the birds either over- or under-consume protein and calcium. The basic principle behind practising choice feeding with laying hens is that individual hens are able to select from the various feed ingredients on offer and compose their own diet, according to their actual needs and production capacity. A choice-feeding system is of particular importance to small poultry producers in developing countries, such as Indonesia, because it can substantially reduce the cost of feed. The system is flexible and can be constructed in such a way that the various needs of a flock of different breeds, including village chickens, under different climates can be met. The system also offers a more effective way to use home-produced grain, such as maize, and by-products, such as rice bran, in developing countries. Because oyster-shell grit is readily available in developing countries at lower cost than limestone, the use of cheaper oyster-shell grit can further benefit small-holders in these countries. These benefits apart, simpler equipment suffices when designing and building a feed mixer on the farm, and transport costs are lower. If whole (unground) grain is used, the intake of which is accompanied by increased efficiency of feed utilisation, the costs of grinding, mixing and many of the handling procedures associated with mash and pellet preparation are eliminated. The choice feedstuffs can all be offered in the current feed distribution systems, either by mixing the ingredients first or by using a bulk bin divided into three compartments.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

RF Receiver Front End for 28.5 GHz Applications on a 70 GHz F-T SiGe BiCMOS Process

This article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system-level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14 5 dB. The receiver operates from a 2 5 V power supply with a total current consumption of 31 mA.

Viability of Two New Mixture Design Methodologies for Self-Consolidating Concrete

This paper presents the results from an experimental study of the technical viability of two mixture designs for self-consolidating concrete (SCC) proposed by two Portuguese researchers in a previous work. The objective was to find the best method to provide the required characteristics of SCC in fresh and hardened states without having to experiment with a large number of mixtures. Five SCC mixtures, each with a volume of 25 L (6.61 gal.) were prepared using a forced mixer with a vertical axis for each of three compressive strength targets: 40, 55, and 70 MPa (5.80, 7.98, and 10.15 ksi). The mixtures' fresh state properties of fluidity, segregation resistance ability, and bleeding and blockage tendency, and their hardened state property of compressive strength were compared. For this study, the following tests were performed. slump-flow, V-funnel, L-box, box, and compressive strength. The results of this study made it possible to identify the most influential factors in the design of the SCC mixtures.

Projecto de um regulador linear de tensão: LDO

Os reguladores de tensão LDO são utilizados intensivamente na actual indústria de electrónica, são uma parte essencial de um bloco de gestão de potência para um SoC. O aumento de produtos portáteis alimentados por baterias levou ao crescimento de soluções totalmente integradas, o que degrada o rendimento dos blocos analógicos que o constituem face às perturbações introduzidas na alimentação. Desta forma, surge a necessidade de procurar soluções cada vez mais optimizadas, impondo assim novas soluções, e/ou melhoramentos dos circuitos de gestão de potência, tendo como objectivo final o aumento do desempenho e da autonomia dos dispositivos electrónicos. Normalmente este tipo de reguladores tem a corrente de saída limitada, devido a problemas de estabilidade associados. Numa tentativa de evitar a instabilidade para as correntes de carga definidas e aumentar o PSRR do mesmo, é apresentado um método de implementação que tem como objectivo melhorar estas características, em que se pretende aumentar o rendimento e melhorar a resposta à variação da carga. No entanto, a técnica apresentada utiliza polarização adaptativa do estágio de potência, o que implica um aumento da corrente de consumo. O regulador LDO foi implementado na tecnologia CMOS UMC 0.18μm e ocupa uma área inferior a 0,2mm2. Os resultados da simulação mostram que o mesmo suporta uma transição de corrente 10μA para 100mA, com uma queda de tensão entre a tensão de alimentação e a tensão de saída inferior a 200mV. A estabilidade é assegurada para todas as correntes de carga. O tempo de estabelecimento é inferior a 6μs e as variações da tensão de saída relativamente a seu valor nominal são inferiores a 5mV. A corrente de consumo varia entre os 140μA até 200μA, o que permite atingir as especificações proposta para um PSRR de 40dB@10kHz.

A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing Maximum Power Point Tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 mu m CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 mu W to the load using 1712 mu W of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

Start-up circuit for low-power indoor light energy harvesting applications

A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm(2). Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

Enhanced Race-to-halt: a leakage-aware energy management approach for dynamic priority systems

With progressing CMOS technology miniaturization, the leakage power consumption starts to dominate the dynamic power consumption. The recent technology trends have equipped the modern embedded processors with the several sleep states and reduced their overhead (energy/time) of the sleep transition. The dynamic voltage frequency scaling (DVFS) potential to save energy is diminishing due to efficient (low overhead) sleep states and increased static (leakage) power consumption. The state-of-the-art research on static power reduction at system level is based on assumptions that cannot easily be integrated into practical systems. We propose a novel enhanced race-to-halt approach (ERTH) to reduce the overall system energy consumption. The exhaustive simulations demonstrate the effectiveness of our approach showing an improvement of up to 8 % over an existing work.

A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA