Um estudo de caso sobre servitiza����o e nacionaliza����o em um fabricante de hardware el��trico

A presente disserta����o tem como principais caracter��sticas, a pesquisa, a an��lise e a proposi����o de um modelo de reflex��o que considera os fatores mais relevantes na inclus��o do processo de presta����o de servi��os em empresas de manufatura de bens, e em particular de empresas que buscam a nacionaliza����o de sua capacidade de fornecimento. Dentro deste conceito de transi����o e incorpora����o de servi��os, que �� denominado pela literatura como ���servitiza����o���, e usando como objeto de pesquisa uma empresa fabricante de hardware el��trico, verificou-se como se deu o planejamento e execu����o da servitiza����o para presta����o de servi��os t��cnicos off-shore, ligados �� cadeia de suprimentos do segmento de Produ����o de ��leo e G��s no mar. Para auxiliar o entendimento sobre o posicionamento da empresa perante servi��os, servitiza����o e nacionaliza����o, foi necess��ria a revis��o bibliogr��fica sobre Requisitos de Conte��do Local, Gest��o de Opera����es em Servi��os, Sistemas Produto-Servi��o, Servitiza����o, e Desenvolvimento de Projeto de Produtos e Servi��os. A partir da an��lise de documenta����o disponibilizada pela empresa, e a compara����o desta com a literatura academica revisada, verificou-se que os modelos propostos pela literatura n��o cont��m todos os elementos necess��rios para aplica����o direta em neg��cios deste tipo. Com base nesta avalia����o, verifica-se quais os fatores mais relevantes para a servitiza����o e prop��e-se um modelo para reflex��o. Modelo este que preenche com elementos mais espec��ficos as lacunas que influenciam negativamente na excel��ncia operacional e na estrat��gia da corpora����o ligada a ind��stria de Petr��leo e G��s Off-shore.

Encontrando o hardware de LIA

Ilustra����o componente do jogo ���LabTecA (http://www.loa.sead.ufscar.br/labteca.php)��� desenvolvido pela equipe do Laborat��rio de Objetos de Aprendizagem da Universidade Federal de S��o Carlos (LOA/UFSCar).

Implementa����o em hardware de uma Rede Neuronal com ummicroprocessador embebido em FPGA

O objectivo deste trabalho �� a implementa����o em hardware de uma Rede Neuronal com um microprocessador embebido, podendo ser um recurso valioso em v��rias ��reas cient��ficas. A import��ncia das implementa����es em hardware deve-se �� flexibilidade, maior desempenho e baixo consumo de energia. Para esta implementa����o foi utilizado o dispositivo FPGA Virtex II Pro XC2VP30 com um MicroBlaze soft core, da Xilinx. O MicroBlaze tem vantagens como a simplicidade no design, sua reutiliza����o e f��cil integra����o com outras tecnologias. A primeira fase do trabalho consistiu num estudo sobre o FPGA, um sistema reconfigur��vel que possui caracter��sticas importantes como a capacidade de executar em paralelo tarefas complexas. Em seguida, desenvolveu-se o c��digo de implementa����o de uma Rede Neuronal Artificial baseado numa linguagem de programa����o de alto n��vel. Na implementa����o da Rede Neuronal aplicou-se, na camada escondida, a fun����o de activa����o tangente hiperb��lica, que serve para fornecer a n��o linearidade �� Rede Neuronal. A implementa����o �� feita usando um tipo de Rede Neuronal que permite apenas liga����es no sentido de sa��da, chamado Redes Neuronais sem realimenta����o (do Ingl��s Feedforward Neural Networks - FNN). Como as Redes Neuronais Artificiais s��o sistemas de processamento de informa����es, e as suas caracter��sticas s��o comuns ��s Redes Neuronais Biol��gicas, aplicaram-se testes na implementa����o em hardware e analisou-se a sua import��ncia, a sua efici��ncia e o seu desempenho. E finalmente, diante dos resultados, fez-se uma an��lise de abordagem e metodologia adoptada e sua viabilidade.

Uma arquitetura distribu��da de hardware e software para controle de um rob�� m��vel aut��nomo

BRITTO, Ricardo S.; MEDEIROS, Adelardo A. D.; ALSINA, Pablo J. Uma arquitetura distribu��da de hardware e software para controle de um rob�� m��vel aut��nomo. In: SIMP��SIO BRASILEIRO DE AUTOMA����O INTELIGENTE,8., 2007, Florian��polis. Anais... Florian��polis: SBAI, 2007.

Uma arquitetura distribu��da de hardware e software para controle de um rob�� m��vel aut��nomo

In this work, we present a hardware-software architecture for controlling the autonomous mobile robot Kapeck. The hardware of the robot is composed of a set of sensors and actuators organized in a CAN bus. Two embedded computers and eigth microcontroller based boards are used in the system. One of the computers hosts the vision system, due to the significant processing needs of this kind of system. The other computer is used to coordinate and access the CAN bus and to accomplish the other activities of the robot. The microcontroller-based boards are used with the sensors and actuators. The robot has this distributed configuration in order to exhibit a good real-time behavior, where the response time and the temporal predictability of the system is important. We adopted the hybrid deliberative-reactive paradigm in the proposed architecture to conciliate the reactive behavior of the sensors-actuators net and the deliberative activities required to accomplish more complex tasks

Metodologia para adapta����o de microarquiteturas microprogramadas soft-core �� uma ISA padr��o: estudo do impacto sobre a complexidade de hardware para o padr��o MIPS

In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments

Uma implementa����o da an��lise de componentes independentes em plataforma de hardware reconfigur��vel

Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation.

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplica����es gen��ricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Acelerando algoritmos de baixo n��vel em vis��o rob��tica com hardware reconfigur��vel

A challenge that remains in the robotics field is how to make a robot to react in real time to visual stimulus. Traditional computer vision algorithms used to overcome this problem are still very expensive taking too long when using common computer processors. Very simple algorithms like image filtering or even mathematical morphology operations may take too long. Researchers have implemented image processing algorithms in high parallelism hardware devices in order to cut down the time spent in the algorithms processing, with good results. By using hardware implemented image processing techniques and a platform oriented system that uses the Nios II Processor we propose an approach that uses the hardware processing and event based programming to simplify the vision based systems while at the same time accelerating some parts of the used algorithms

Hardware implementation of an analog neural nonderivative optimizer

Analog neural systems that can automatically find the minimum value of the outputs of unknown analog systems, described by convex functions, are studied. When information about derivative or gradient are not used, these systems are called analog nonderivative optimizers. An electronic circuit for the analog neural nonderivative optimizer proposed by Teixeira and Zak, and its simulation with software PSPICE, is presented. With the simulation results and hardware implementation of the system, the validity of the proposed optimizer can be verified. These results are original, from the best of the authors knowledge.

Implementa����o Hardware/Software da estima����o de movimento segundo o padr��o H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Gera����o autom��tica de hardware apartir de especifica����es formais: estendendo uma abordagem de tradu����o

A remo����o de inconsist��ncias em um projeto �� menos custosa quando realizadas nas etapas iniciais da sua concep����o. A utiliza����o de M��todos Formais melhora a compreens��o dos sistemas al��m de possuir diversas t��cnicas, como a especifica����o e verifica����o formal, para identificar essas inconsist��ncias nas etapas iniciais de um projeto. Por��m, a transforma����o de uma especifica����o formal para uma linguagem de programa����o �� uma tarefa n��o trivial. Quando feita manualmente, �� uma tarefa pass��vel da inser����o de erros. O uso de ferramentas que auxiliem esta etapa pode proporcionar grandes benef��cios ao produto final a ser desenvolvido. Este trabalho prop��e a extens��o de uma ferramenta cujo foco �� a tradu����o autom��tica de especifica����es em CSPm para Handel-C. CSP �� uma linguagem de descri����o formal adequada para trabalhar com sistemas concorrentes. Handel-C �� uma linguagem de programa����o cujo resultado pode ser compilado diretamente para FPGA's. A extens��o consiste no aumento no n��mero de operadores CSPm aceitos pela ferramenta, permitindo ao usu��rio definir processos locais, renomear canais e utilizar guarda booleana em escolhas externas. Al��m disto, propomos tamb��m a implementa����o de um protocolo de comunica����o que elimina algumas restri����es da composi����o paralela de processos na tradu����o para Handel-C, permitindo que a comunica����o entre m��ltiplos processos possa ser mapeada de maneira consistente e que a mesma somente ocorra quando for autorizada.

Gera����o autom��tica de hardware a partir de especifica����es formais: estendendo uma abordagem de tradu����o

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification

Utilizando programa����o orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC

New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the modularity of object-oriented and structured languages such Java, C++ and C. Thus, one can expect that, using AOP, one can improve the understanding of the hardware systems under design, as well as make its components more reusable and easier to maintain. We apply AOP in applications developed using the SystemC library. Several examples will be presented illustrating how to combine AOP and SystemC. During the presentation of these examples, the benefits of this new approach will also be discussed