999 resultados para fluorescence en voltage imposé
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This paper presents a voltage and power quality enhancement scheme for a doubly-fed induction generator (DFIG) wind farm during variable wind conditions. The wind profiles were derived considering the measured data at a DFIG wind farm located in Northern Ireland (NI). The aggregated DFIG wind farm model was validated using measured data at a wind farm during variable generation. The voltage control strategy was developed considering the X/R ratio of the wind farm feeder which connects the wind farm and the grid. The performance of the proposed strategy was evaluated for different X/R ratios, and wind profiles with different characteristics. The impact of flicker propagation along the wind farm feeder and effectiveness of the proposed strategy is also evaluated with consumer loads connected to the wind farm feeder. It is shown that voltage variability and short-term flicker severity is significantly reduced following implementation of the novel strategy described.
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This paper examines power quality benchmarks in the electricity supply industry (ESI) and impact of standards for the reduction of voltage dip incidents. The paper considers adherence to particular standards and is supported by several case studies from incidents where voltage dips have been detected and assessed by the power systems division of Scottish Power and where improvements have been implemented to help militate against subsequent incidents.
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The change in the Pt electronic structure following the adsorption of an a,ß-unsaturated aldehyde and ketone was followed by in situ HERFD-XANES in the liquid phase. The resulting shift in the Pt Fermi energy is in good agreement with the molecule adsorption energy trends calculated by DFT and provides insight into the reaction selectivity.
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Rapid and robust methods are required to quantify the effect of hydrodynamic shear on protein conformation change. We evaluated such strategies in this work and found that the binding of the fluorescent probe 4,4'-dianilino-1, 1'-binaphthyl-5,5'-disulfonic acid (bis-ANS) to hydrophobic pockets in the blood protein von Willebrand factor (VWF) is enhanced upon the application of fluid shear to the isolated protein. Significant structural changes were observed when the protein was sheared at shear rates >= 6000/s for similar to 3.5 min. The binding of bis-ANS to multimeric VWF, but not dimeric VWF or control protein bovine serum albumin, was enhanced upon fluid shear application. Thus, high-molecular-weight VWF is more susceptible to conformation change upon tensile loading. Although bis-ANS itself did not alter the conformation of VWF, it stabilized protein conformation once it bound the sheared molecule. Bis-ANS binding to VWF was reduced when the sheared protein was allowed to relax before dye addition. Taken together with functional data in the literature, our results suggest that shear-induced conformation changes in VWF reported by bis-ANS correlate well with the normal function of the protein under physiological/pathological fluid flow conditions. Further, this study introduces the fluorescent dye bis-ANS as a tool that may be useful in studies of shear-induced protein conformation change.
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The design, development and evaluation of an optical fibre pH sensor for monitoring pH in the alkaline region are discussed in detail in this paper. The design of this specific pH sensor is based on the pH induced change in fluorescence intensity of a coumarin imidazole dye which is covalently attached to a polymer network and then fixed to the distal end of an optical fibre. The sensor provides a response over a pH range of 10.0–13.2 with an acceptable response rate of around 50 min, having shown a very good stability over a period of longer than 20 months thus far. The sensor has also demonstrated little cross-sensitivity to ionic strength (IS) and also excellent photostability through a series of laboratory tests. These features make this type of sensor potentially well suited for in situ long term monitoring of pH in concrete structures, to enhance structural monitoring in the civil engineering sector
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Two models that can predict the voltage-dependent scattering from liquid crystal (LC)-based reflectarray cells are presented. The validity of both numerical techniques is demonstrated using measured results in the frequency range 94-110 GHz. The most rigorous approach models, for each voltage, the inhomogeneous and anisotropic permittivity of the LC as a stratified media in the direction of the biasing field. This accounts for the different tilt angles of the LC molecules inside the cell calculated from the solution of the elastic problem. The other model is based on an effective homogeneous permittivity tensor that corresponds to the average tilt angle along the longitudinal direction for each biasing voltage. In this model, convergence problems associated with the longitudinal inhomogeneity are avoided, and the computation efficiency is improved. Both models provide a correspondence between the reflection coefficient (losses and phase-shift) of the LC-based reflectarray cell and the value of biasing voltage, which can be used to design beam scanning reflectarrays. The accuracy and the efficiency of both models are also analyzed and discussed.
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Reconfigurable bistate metasurfaces composed of interwoven spiral arrays with embedded pin diodes are proposed for single and dual polarisation operation. The switching capability is enabled by pin diodes that change the array response between transmission and reflection modes at the specified frequencies. The spiral conductors forming the metasurface also supply the dc bias for controlling pin diodes, thus avoiding the need of additional bias circuitry that can cause parasitic interference and affect the metasurface response. The simulation results show that proposed active metasurfaces exhibit good isolation between transmission and reflection states, while retaining excellent angular and polarisation stability with the large fractional bandwidth (FBW) inherent to the original passive arrays. © 2014 A. Vallecchi et al.
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Skin fluorescence (SF) is a non-invasive marker of AGEs and is associated with the long-term complications of diabetes. SF increases with age and is also greater among individuals with diabetes. A familial correlation of SF suggests that genetics may play a role. We therefore performed parallel genome-wide association studies of SF in two cohorts.
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This paper is concerned with the voltage and reactive power issues surrounding the connection of Distributed Generation (DG) on the low-voltage (LV) distribution network. The presented system-wide voltage control algorithm consists of three stages. Firstly available reactive power reserves are utilized. Then, if required, DG active power output is curtailed. Finally, curtailment of non-critical site demand is considered. The control methodology is tested on a variant of the 13-bus IEEE Node Radial Distribution Test Feeder. The presented control algorithm demonstrated that the distribution system operator (DSO) can maintain voltage levels within a desired statutory range by dispatching reactive power from DG or network devices. The practical application of the control strategy is discussed.
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In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration system level interactions and ensuring that under any change of operating conditions only the "lesscrucial" computations, that contribute less to block/system output quality, are affected. The design methodology applied to a DCT/IDCT system shows large power benefits (up to 69%) at reasonable image quality while tolerating errors induced by varying operating conditions (VOS, process variations, channel noise). Interestingly, the proposed IDCT scheme conceals channel noise at scaled voltages. ©2009 IEEE.
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Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.
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In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.
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In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.
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In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.