Integration of III-V materials on Silicon Substrates for Multi-junction Solar Cell Applications

The work presented here aims to reduce the cost of multijunction solar cell technology by developing ways to manufacture them on cheap substrates such as silicon. In particular, our main objective is the growth of III-V semiconductors on silicon substrates for photovoltaic applications. The goal is to create a GaAsP/Si virtual substrates onto which other III-V cells could be integrated with an interesting efficiency potential. This technology involves several challenges due to the difficulty of growing III-V materials on silicon. In this paper, our first work done aimed at developing such structure is presented. It was focused on the development of phosphorus diffusion models on silicon and on the preparation of an optimal silicon surface to grow on it III-V materials.

MBE growth and characterization of InGaN-based films and nanocolumns on Silicon substrates and GaN templates

InN layers: MBE growth issues Growth of InN-based thin films: InN/InGaN QWS on GaN Growth of InN-based nanorods ● Self Self-assembled assembled InN InN nanorods nanorods onon different different substrates substrates ● Self-assembled InGaN nanorods ● Broad- Broad-emission emission nanostructures ● Self Self--assembled assembled InGaN InGaN--based based Qdisks Qdisks ● Selective area growth (SAG) of InGaN Qdisks

Impact of MOVPE Environment on Silicon Substrates for III-V-on-Si Multijunction Solar Cells

With the final goal of integrating III-V materials to silicon for tandem solar cells, the influence of the metal-organic vapor phase epitaxy (MOVPE) environment on the minority carrier properties of silicon wafers has been evaluated. These properties will essentially determine the photovoltaic performance of the bottom cell in a III-V-on-Si tandem solar cell device. A comparison of the base minority carrier lifetimes obtained for different thermal processes carried out in a MOVPE reactor on Czochralski silicon wafers has been carried out. The effect of the formation of the emitter by phosphorus diffusion has also been evaluated.

Understanding phosphorus diffusion into silicon in a MOVPE environment for III-V on silicon solar cells

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III?V materials on silicon for photovoltaic applications. When manufacturing a multi-junction solar cell on silicon, one of the first processes to be addressed is the development of the bottom subcell and, in particular, the formation of its emitter. In this study, we analyze, both experimentally and by simulations, the formation of the emitter as a result of phosphorus diffusion that takes place during the first stages of the epitaxial growth of the solar cell. Different conditions for the Metal-Organic Vapor Phase Epitaxy (MOVPE) process have been evaluated to understand the impact of each parameter, namely, temperature, phosphine partial pressure, time exposure and memory effects in the final diffusion profiles obtained. A model based on SSupremIV process simulator has been developed and validated against experimental profiles measured by ECV and SIMS to calculate P diffusion profiles in silicon formed in a MOVPE environment taking in consideration all these factors.

Optimization of the silicon subcell for III-V on silicon multijunction solar cells: key differences with conventional silicon technology

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon (Si) bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on Si for photovoltaic (PV) applications. Such integration would offer a cost breakthrough for PV technology, unifying the low cost of Si and the efficiency potential of III-V multijunction solar cells. The optimization of the Si solar cells properties in flat-plate PV technology is well-known; nevertheless, it has been proven that the behavior of Si substrates is different when processed in an MOVPE reactor In this study, we analyze several factors influencing the bottom subcell performance, namely, 1) the emitter formation as a result of phosphorus diffusion; 2) the passivation quality provided by the GaP nucleation layer; and 3) the process impact on the bottom subcell PV properties.

Influence of PH3 exposure on silicon substrate morphology in the MOVPE growth of III-V on silicon multijunction solar cells

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on silicon for photovoltaic applications. One of the first issues to be considered in the development of this structure will be the strategy to create the silicon emitter of the bottom subcell. In this study, we explore the possibility of forming the silicon emitter by phosphorus diffusion (i.e. exposing the wafer to PH3 in a MOVPE reactor) and still obtain good surface morphologies to achieve a successful III-V heteroepitaxy as occurs in conventional III-V on germanium solar cell technology. Consequently, we explore the parameter space (PH3 partial pressure, time and temperature) that is needed to create optimized emitter designs and assess the impact of such treatments on surface morphology using atomic force microscopy. Although a strong degradation of surface morphology caused by prolonged exposure of silicon to PH3 is corroborated, it is also shown that subsequent anneals under H-2 can recover silicon surface morphology and minimize its RMS roughness and the presence of pits and spikes.

MOVPE growth of III-V semiconductors on silicon for third generation solar cells

Esta Tesis trata sobre el desarrollo y crecimiento -mediante tecnología MOVPE (del inglés: MetalOrganic Vapor Phase Epitaxy)- de células solares híbridas de semiconductores III-V sobre substratos de silicio. Esta integración pretende ofrecer una alternativa a las células actuales de III-V, que, si bien ostentan el récord de eficiencia en dispositivos fotovoltaicos, su coste es, a día de hoy, demasiado elevado para ser económicamente competitivo frente a las células convencionales de silicio. De este modo, este proyecto trata de conjugar el potencial de alta eficiencia ya demostrado por los semiconductores III-V en arquitecturas de células fotovoltaicas multiunión con el bajo coste, la disponibilidad y la abundancia del silicio. La integración de semiconductores III-V sobre substratos de silicio puede afrontarse a través de diferentes aproximaciones. En esta Tesis se ha optado por el desarrollo de células solares metamórficas de doble unión de GaAsP/Si. Mediante esta técnica, la transición entre los parámetros de red de ambos materiales se consigue por medio de la formación de defectos cristalográficos (mayoritariamente dislocaciones). La idea es confinar estos defectos durante el crecimiento de sucesivas capas graduales en composición para que la superficie final tenga, por un lado, una buena calidad estructural, y por otro, un parámetro de red adecuado. Numerosos grupos de investigación han dirigido sus esfuerzos en los últimos años en desarrollar una estructura similar a la que aquí proponemos. La mayoría de éstos se han centrado en entender los retos asociados al crecimiento de materiales III-V, con el fin de conseguir un material de alta calidad cristalográfica. Sin embargo, prácticamente ninguno de estos grupos ha prestado especial atención al desarrollo y optimización de la célula inferior de silicio, cuyo papel va a ser de gran relevancia en el funcionamiento de la célula completa. De esta forma, y con el fin de completar el trabajo hecho hasta el momento en el desarrollo de células de III-V sobre silicio, la presente Tesis se centra, fundamentalmente, en el diseño y optimización de la célula inferior de silicio, para extraer su máximo potencial. Este trabajo se ha estructurado en seis capítulos, ordenados de acuerdo al desarrollo natural de la célula inferior. Tras un capítulo de introducción al crecimiento de semiconductores III-V sobre Si, en el que se describen las diferentes alternativas para su integración; nos ocupamos de la parte experimental, comenzando con una extensa descripción y caracterización de los substratos de silicio. De este modo, en el Capítulo 2 se analizan con exhaustividad los diferentes tratamientos (tanto químicos como térmicos) que deben seguir éstos para garantizar una superficie óptima sobre la que crecer epitaxialmente el resto de la estructura. Ya centrados en el diseño de la célula inferior, el Capítulo 3 aborda la formación de la unión p-n. En primer lugar se analiza qué configuración de emisor (en términos de dopaje y espesor) es la más adecuada para sacar el máximo rendimiento de la célula inferior. En este primer estudio se compara entre las diferentes alternativas existentes para la creación del emisor, evaluando las ventajas e inconvenientes que cada aproximación ofrece frente al resto. Tras ello, se presenta un modelo teórico capaz de simular el proceso de difusión de fosforo en silicio en un entorno MOVPE por medio del software Silvaco. Mediante este modelo teórico podemos determinar qué condiciones experimentales son necesarias para conseguir un emisor con el diseño seleccionado. Finalmente, estos modelos serán validados y constatados experimentalmente mediante la caracterización por técnicas analíticas (i.e. ECV o SIMS) de uniones p-n con emisores difundidos. Uno de los principales problemas asociados a la formación del emisor por difusión de fósforo, es la degradación superficial del substrato como consecuencia de su exposición a grandes concentraciones de fosfina (fuente de fósforo). En efecto, la rugosidad del silicio debe ser minuciosamente controlada, puesto que éste servirá de base para el posterior crecimiento epitaxial y por tanto debe presentar una superficie prístina para evitar una degradación morfológica y cristalográfica de las capas superiores. En este sentido, el Capítulo 4 incluye un análisis exhaustivo sobre la degradación morfológica de los substratos de silicio durante la formación del emisor. Además, se proponen diferentes alternativas para la recuperación de la superficie con el fin de conseguir rugosidades sub-nanométricas, que no comprometan la calidad del crecimiento epitaxial. Finalmente, a través de desarrollos teóricos, se establecerá una correlación entre la degradación morfológica (observada experimentalmente) con el perfil de difusión del fósforo en el silicio y por tanto, con las características del emisor. Una vez concluida la formación de la unión p-n propiamente dicha, se abordan los problemas relacionados con el crecimiento de la capa de nucleación de GaP. Por un lado, esta capa será la encargada de pasivar la subcélula de silicio, por lo que su crecimiento debe ser regular y homogéneo para que la superficie de silicio quede totalmente pasivada, de tal forma que la velocidad de recombinación superficial en la interfaz GaP/Si sea mínima. Por otro lado, su crecimiento debe ser tal que minimice la aparición de los defectos típicos de una heteroepitaxia de una capa polar sobre un substrato no polar -denominados dominios de antifase-. En el Capítulo 5 se exploran diferentes rutinas de nucleación, dentro del gran abanico de posibilidades existentes, para conseguir una capa de GaP con una buena calidad morfológica y estructural, que será analizada mediante diversas técnicas de caracterización microscópicas. La última parte de esta Tesis está dedicada al estudio de las propiedades fotovoltaicas de la célula inferior. En ella se analiza la evolución de los tiempos de vida de portadores minoritarios de la base durante dos etapas claves en el desarrollo de la estructura Ill-V/Si: la formación de la célula inferior y el crecimiento de las capas III-V. Este estudio se ha llevado a cabo en colaboración con la Universidad de Ohio, que cuentan con una gran experiencia en el crecimiento de materiales III-V sobre silicio. Esta tesis concluye destacando las conclusiones globales del trabajo realizado y proponiendo diversas líneas de trabajo a emprender en el futuro. ABSTRACT This thesis pursues the development and growth of hybrid solar cells -through Metal Organic Vapor Phase Epitaxy (MOVPE)- formed by III-V semiconductors on silicon substrates. This integration aims to provide an alternative to current III-V cells, which, despite hold the efficiency record for photovoltaic devices, their cost is, today, too high to be economically competitive to conventional silicon cells. Accordingly, the target of this project is to link the already demonstrated efficiency potential of III-V semiconductor multijunction solar cell architectures with the low cost and unconstrained availability of silicon substrates. Within the existing alternatives for the integration of III-V semiconductors on silicon substrates, this thesis is based on the metamorphic approach for the development of GaAsP/Si dual-junction solar cells. In this approach, the accommodation of the lattice mismatch is handle through the appearance of crystallographic defects (namely dislocations), which will be confined through the incorporation of a graded buffer layer. The resulting surface will have, on the one hand a good structural quality; and on the other hand the desired lattice parameter. Different research groups have been working in the last years in a structure similar to the one here described, being most of their efforts directed towards the optimization of the heteroepitaxial growth of III-V compounds on Si, with the primary goal of minimizing the appearance of crystal defects. However, none of these groups has paid much attention to the development and optimization of the bottom silicon cell, which, indeed, will play an important role on the overall solar cell performance. In this respect, the idea of this thesis is to complete the work done so far in this field by focusing on the design and optimization of the bottom silicon cell, to harness its efficiency. This work is divided into six chapters, organized according to the natural progress of the bottom cell development. After a brief introduction to the growth of III-V semiconductors on Si substrates, pointing out the different alternatives for their integration; we move to the experimental part, which is initiated by an extensive description and characterization of silicon substrates -the base of the III-V structure-. In this chapter, a comprehensive analysis of the different treatments (chemical and thermal) required for preparing silicon surfaces for subsequent epitaxial growth is presented. Next step on the development of the bottom cell is the formation of the p-n junction itself, which is faced in Chapter 3. Firstly, the optimization of the emitter configuration (in terms of doping and thickness) is handling by analytic models. This study includes a comparison between the different alternatives for the emitter formation, evaluating the advantages and disadvantages of each approach. After the theoretical design of the emitter, it is defined (through the modeling of the P-in-Si diffusion process) a practical parameter space for the experimental implementation of this emitter configuration. The characterization of these emitters through different analytical tools (i.e. ECV or SIMS) will validate and provide experimental support for the theoretical models. A side effect of the formation of the emitter by P diffusion is the roughening of the Si surface. Accordingly, once the p-n junction is formed, it is necessary to ensure that the Si surface is smooth enough and clean for subsequent phases. Indeed, the roughness of the Si must be carefully controlled since it will be the basis for the epitaxial growth. Accordingly, after quantifying (experimentally and by theoretical models) the impact of the phosphorus on the silicon surface morphology, different alternatives for the recovery of the surface are proposed in order to achieve a sub-nanometer roughness which does not endanger the quality of the incoming III-V layers. Moving a step further in the development of the Ill-V/Si structure implies to address the challenges associated to the GaP on Si nucleation. On the one hand, this layer will provide surface passivation to the emitter. In this sense, the growth of the III-V layer must be homogeneous and continuous so the Si emitter gets fully passivated, providing a minimal surface recombination velocity at the interface. On the other hand, the growth should be such that the appearance of typical defects related to the growth of a polar layer on a non-polar substrate is minimized. Chapter 5 includes an exhaustive study of the GaP on Si nucleation process, exploring different nucleation routines for achieving a high morphological and structural quality, which will be characterized by means of different microscopy techniques. Finally, an extensive study of the photovoltaic properties of the bottom cell and its evolution during key phases in the fabrication of a MOCVD-grown III-V-on-Si epitaxial structure (i.e. the formation of the bottom cell; and the growth of III-V layers) will be presented in the last part of this thesis. This study was conducted in collaboration with The Ohio State University, who has extensive experience in the growth of III-V materials on silicon. This thesis concludes by highlighting the overall conclusions of the presented work and proposing different lines of work to be undertaken in the future.

Ellipsometric study of nematic alignment on silicon oxides for display

Vertical Alignment Nematics (VANs) displays are a form of LCDs in which the liquid crystals naturally align vertically to the glass substrates. In spite of their name, the liquid crystal (LC) director is never exactly vertical, rather it always show a small angle with the normal to the sample plane called tilt that may vary throughout the cell bulk. Its values are ultimately determined by the pretilt, defined as the tilt angle on the surfaces in the absence of voltage.

Impact of metal-organic vapor phase epitaxy environment on silicon bulk lifetime for III–V-on-Si multijunction solar cells

With the final goal of integrating III-V materials on silicon substrates for tandem solar cells, the influence of the Metal-Organic Vapor Phase Epitaxy (MOVPE) environment on the minority carrier properties of silicon wafers has been evaluated. These properties will essentially determine the photovoltaic performance of the bottom cell in a III-V-on-Si tandem solar cell. A comparison of the base minority carrier lifetimes obtained for different thermal processes carried out in a MOVPE reactor on Czochralski silicon wafers has been carried out. An important degradation of minority carrier lifetime during the surface preparation (i.e. H2 anneal) has been observed. Three different mechanisms have been proposed for explaining this behavior: 1) the introduction of extrinsic impurities coming from the reactor; 2) the activation of intrinsic lifetime killing impurities coming from the wafer itself; and finally, 3) the formation of crystal defects, which eventually become recombination centers. The effect of the emitter formation by phosphorus diffusion has also been evaluated. In this sense, it has been reported that lifetime can be recovered during the emitter formation either by the effect of the P on extracting impurities, or by the role of the atomic hydrogen on passivating the defects.

Desorption/ionization on silicon (DIOS): A diverse mass spectrometry platform for protein characterization

Since the advent of matrix-assisted laser desorption/ionization and electrospray ionization, mass spectrometry has played an increasingly important role in protein functional characterization, identification, and structural analysis. Expanding this role, desorption/ionization on silicon (DIOS) is a new approach that allows for the analysis of proteins and related small molecules. Despite the absence of matrix, DIOS-MS yields little or no fragmentation and is relatively tolerant of moderate amounts of contaminants commonly found in biological samples. Here, functional assays were performed on an esterase, a glycosidase, a lipase, as well as exo- and endoproteases by using enzyme-specific substrates. Enzyme activity also was monitored in the presence of inhibitors, successfully demonstrating the ability of DIOS to be used as an inhibitor screen. Because DIOS is a matrix-free desorption technique, it also can be used as a platform for multiple analyses to be performed on the same protein. This unique advantage was demonstrated with acetylcholine esterase for qualitative and quantitative characterization and also by its subsequent identification directly from the DIOS platform.

A thermally wavelength-tunable photonic switch based on silicon microring resonator

Silicon photonics is a very promising technology for future low-cost high-bandwidth optical telecommunication applications down to the chip level. This is due to the high degree of integration, high optical bandwidth and large speed coupled with the development of a wide range of integrated optical functions. Silicon-based microring resonators are a key building block that can be used to realize many optical functions such as switching, multiplexing, demultiplaxing and detection of optical wave. The ability to tune the resonances of the microring resonators is highly desirable in many of their applications. In this work, the study and application of a thermally wavelength-tunable photonic switch based on silicon microring resonator is presented. Devices with 10μm diameter were systematically studied and used in the design. Its resonance wavelength was tuned by thermally induced refractive index change using a designed local micro-heater. While thermo-optic tuning has moderate speed compared with electro-optic and all-optic tuning, with silicon’s high thermo-optic coefficient, a much wider wavelength tunable range can be realized. The device design was verified and optimized by optical and thermal simulations. The fabrication and characterization of the device was also implemented. The microring resonator has a measured FSR of ∼18 nm, FWHM in the range 0.1-0.2 nm and Q around 10,000. A wide tunable range (>6.4 nm) was achieved with the switch, which enables dense wavelength division multiplexing (DWDM) with a channel space of 0.2nm. The time response of the switch was tested on the order of 10 μs with a low power consumption of ∼11.9mW/nm. The measured results are in agreement with the simulations. Important applications using the tunable photonic switch were demonstrated in this work. 1×4 and 4×4 reconfigurable photonic switch were implemented by using multiple switches with a common bus waveguide. The results suggest the feasibility of on-chip DWDM for the development of large-scale integrated photonics. Using the tunable switch for output wavelength control, a fiber laser was demonstrated with Erbium-doped fiber amplifier as the gain media. For the first time, this approach integrated on-chip silicon photonic wavelength control.

A Thermally Wavelength-tunable Photonic Switch Based on Silicon Microring Resonator

Silicon photonics is a very promising technology for future low-cost high-bandwidth optical telecommunication applications down to the chip level. This is due to the high degree of integration, high optical bandwidth and large speed coupled with the development of a wide range of integrated optical functions. Silicon-based microring resonators are a key building block that can be used to realize many optical functions such as switching, multiplexing, demultiplaxing and detection of optical wave. The ability to tune the resonances of the microring resonators is highly desirable in many of their applications. In this work, the study and application of a thermally wavelength-tunable photonic switch based on silicon microring resonator is presented. Devices with 10µm diameter were systematically studied and used in the design. Its resonance wavelength was tuned by thermally induced refractive index change using a designed local micro-heater. While thermo-optic tuning has moderate speed compared with electro-optic and all-optic tuning, with silicon’s high thermo-optic coefficient, a much wider wavelength tunable range can be realized. The device design was verified and optimized by optical and thermal simulations. The fabrication and characterization of the device was also implemented. The microring resonator has a measured FSR of ~18 nm, FWHM in the range 0.1-0.2 nm and Q around 10,000. A wide tunable range (>6.4 nm) was achieved with the switch, which enables dense wavelength division multiplexing (DWDM) with a channel space of 0.2nm. The time response of the switch was tested on the order of 10 us with a low power consumption of ~11.9mW/nm. The measured results are in agreement with the simulations. Important applications using the tunable photonic switch were demonstrated in this work. 1×4 and 4×4 reconfigurable photonic switch were implemented by using multiple switches with a common bus waveguide. The results suggest the feasibility of on-chip DWDM for the development of large-scale integrated photonics. Using the tunable switch for output wavelength control, a fiber laser was demonstrated with Erbium-doped fiber amplifier as the gain media. For the first time, this approach integrated on-chip silicon photonic wavelength control.

Heterogeneously grown tunable group-IV laser on silicon

Tunable tensile-strained germanium (epsilon-Ge) thin films on GaAs and heterogeneously integrated on silicon (Si) have been demonstrated using graded III-V buffer architectures grown by molecular beam epitaxy (MBE). epsilon-Ge epilayers with tunable strain from 0% to 1.95% on GaAs and 0% to 1.11% on Si were realized utilizing MBE. The detailed structural, morphological, band alignment and optical properties of these highly tensile-strained Ge materials were characterized to establish a pathway for wavelength-tunable laser emission from 1.55 μm to 2.1 μm. High-resolution X-ray analysis confirmed pseudomorphic epsilon-Ge epitaxy in which the amount of strain varied linearly as a function of indium alloy composition in the InxGa1-xAs buffer. Cross-sectional transmission electron microscopic analysis demonstrated a sharp heterointerface between the epsilon-Ge and the InxGa1-xAs layer and confirmed the strain state of the epsilon-Ge epilayer. Lowtemperature micro-photoluminescence measurements confirmed both direct and indirect bandgap radiative recombination between the Γ and L valleys of Ge to the light-hole valence band, with L-lh bandgaps of 0.68 eV and 0.65 eV demonstrated for the 0.82% and 1.11% epsilon-Ge on Si, respectively. The highly epsilon-Ge exhibited a direct bandgap, and wavelength-tunable emission was observed for all samples on both GaAs and Si. Successful heterogeneous integration of tunable epsilon-Ge quantum wells on Si paves the way for the implementation of monolithic heterogeneous devices on Si.