Multiplier-less realization of a poly-phase filter using LUT-based FPGAs

In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.

Development of operator independent bone cement vacuum mixing system for joint replacement surgery,

(2006) Vol. 35 No. 8 317

The maximal C*-algebra of quotients as an operator bimodule

We establish a description of the maximal C*-algebra of quotients of a unital C*-algebra A as a direct limit of spaces of completely bounded bimodule homomorphisms from certain operator submodules of the Haagerup tensor product of A with itself labelled by the essential closed right ideals of A into A. In addition the invariance of the construction of the maximal C*-algebra of quotients under strong Morita equivalence is proved.

Stable isomorphism of dual operator spaces

We prove that two dual operator spaces $X$ and $Y$ are stably isomorphic if and only if there exist completely isometric normal representations $phi$ and $psi$ of $X$ and $Y$, respectively, and ternary rings of operators $M_1, M_2$ such that $phi (X)= [M_2^*psi (Y)M_1]^{-w^*}$ and $psi (Y)=[M_2phi (X)M_1^*].$ We prove that this is equivalent to certain canonical dual operator algebras associated with the operator spaces being stably isomorphic. We apply these operator space results to prove that certain dual operator algebras are stably isomorphic if and only if they are isomorphic. We provide examples motivated by CSL algebra theory.

Power Efficient Dynamic-Range Utilisation for DSP On FPGA

A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.

Power Efficient DSP Datapath Configuration Methodology for FPGA

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

Neural network forecasts of input-output technology

A significant part of the literature on input-output (IO) analysis is dedicated to the development and application of methodologies forecasting and updating technology coefficients and multipliers. Prominent among such techniques is the RAS method, while more information demanding econometric methods, as well as other less promising ones, have been proposed. However, there has been little interest expressed in the use of more modern and often more innovative methods, such as neural networks in IO analysis in general. This study constructs, proposes and applies a Backpropagation Neural Network (BPN) with the purpose of forecasting IO technology coefficients and subsequently multipliers. The RAS method is also applied on the same set of UK IO tables, and the discussion of results of both methods is accompanied by a comparative analysis. The results show that the BPN offers a valid alternative way of IO technology forecasting and many forecasts were more accurate using this method. Overall, however, the RAS method outperformed the BPN but the difference is rather small to be systematic and there are further ways to improve the performance of the BPN.

Separable Banach lattices on which every bounded linear operator is regular

We give a complete description of those separable Banach lattices E with the property that every bounded linear from E into itself is the difference of two positive operators.

Operator hyperreflexivity of subspace lattices

We introduce and study the notion of operator hyperreflexivity of subspace lattices. This notion is a natural analogue of the operator reflexivity and is related to hyperreflexivity of subspace lattices introduced by Davidson and Harrison.