Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Small-Signal Equivalent-Circuit Model and Characterization of 1.55-mu m Buried Tunnel Junction Vertical-Cavity Surface-Emitting Lasers

The work was supported in part by the National Natural Science Foundation of China under Grant 60536010, Grant 60606019, Grant 60777029, and Grant 60820106004, and in part by the National Basic Research Program of China under Grant 2006CB604902, Grant 2006CB302806, and Grant 2006dfa11880.

Rate-equation-based circuit model of high-speed semiconductor lasers

Based oil rare equations of semiconductor laser, a symbolically-defined model for optical transmission system performance evaluation and network characterization in both time- and frequency domains is presented. The steady-state and small-signal characteristics, such as current-photon density curve, current-voltage curve, and input impedance, call be predicted from this model. Two important dynamic characteristics, second-order harmonic distortion and two-tone third-order intermodulation products, are evaluated under different driving conditions. Experiments show that the simulated results agree well with the published data. (c) 2007 Wiley Periodicals, Inc.

A small signal equivalent circuit model for resonant tunnelling diode

We report a resonant tunneling diode (RTD) small signal equivalent circuit model consisting of quantum capacitance and quantum inductance. The model is verified through the actual InAs/In0.53Ga0.47As/AlAs RTD fabricated on an InP substrate. Model parameters are extracted by fitting the equivalent circuit model with ac measurement data in three different regions of RTD current-voltage (I-V) characteristics. The electron lifetime, representing the average time that the carriers remain in the quasibound states during the tunneling process, is also calculated to be 2.09 ps.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Quantum fluctuation of dissipative mesoscopic capacitance coupling circuit

The quantum wave function and the corresponding energy levels of the dissipative mesoscopic capacitance coupling circuits are obtained by using unitary and linear transformations. The quantum fluctuation of charge and current in an arbitrary eigenstate of the system have been also given. The results show that the fluctuation of charge and current depends on not only the eigenstate but also the electronic device parameters.

Double-wave function of RLC circuit after quantization

Quantization of RLC circuit is given and described by a double-wave function. A comparison between classical limit result and those of classical theory is made.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Simulation of single electronic device and robust circuit construction

The article mainly focuses on the simulation of the single electron device and circuit. The orthodox model of single electronic device is introduced and the simulation with Matlab and Pspice is illustrated in the article. Moreover, the built of robust circuit using single electronic according to neural network is done and the simulation is also included in the paper. The result shows that neural network added with proper redundancy is an available candidate for single electron device circuit. The proposed structure is also promising for the realization of low ultra-low power consumption and solution of transient device failure.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.