On the concept of electrical impedance for an electrolytic cell

The analysis of the electrical impedance of an electrolytic cell in the shape of a slab is performed. We have solved, numerically, the differential equations governing the phenomenon of the redistribution of the ions in the presence of an external electric field, and compared the results with the ones obtained by solving the linear approximation of these equations. The control parameters in our study are the amplitude and the frequency of the applied voltage, assumed a simple harmonic function of the time. We show that for the large amplitudes of the applied voltage, the actual current is no longer harmonic at low frequencies. From this result it follows that the concept of electrical impedance of a cell is a useful quantity only in the case where the linear approximation of the fundamental equations of problem work well.

The role of an insulating surface layer on the relaxation time of the ionic redistribution in an electrolytic cell

We analyze the influence of a surface dielectric layer on the transient phenomena related to the ionic redistribution in an electrolytic cell submitted to a step-like external voltage. The adsorption-desorption phenomenon is taken into account in the famework of the Gouy-Chapman approximation, where the ions are assumed dimensionless. In the limit of small amplitude of the applied voltage, where the equations of the problem can be linearized, we obtain an analytical solution for the surface densities of ions, for the electrical potential and for the relaxation time for the transient phenomena. In the general case, when the linearized analysis is no longer valid, the solution of the problem is obtained numerically. The role of the thickness of the dielectric layer on the relaxation time is also discussed.

Uma fonte chaveada de 50kW com correção de fator de potência para alimentação de uma tocha de plasma Indutiva utilizando técnicas de controle digital

This work deals with the development of an experimental study on a power supply of high frequency that provides the toch plasmica to be implemented in PLASPETRO project, which consists of two static converters developed by using Insulated Gate Bipolar Transistor (IGBT). The drivers used to control these keys are triggered by Digital Signal Processor (DSP) through optical fibers to reduce problems with electromagnetic interference (EMI). The first stage consists of a pre-regulator in the form of an AC to DC converter with three-phase boost power factor correction which is the main theme of this work, while the second is the source of high frequency itself. A series-resonant inverter consists of four (4) cell inverters operating in a frequency around 115 kHz each one in soft switching mode, alternating itself to supply the load (plasma torch) an alternating current with a frequency of 450 kHz. The first stage has the function of providing the series-resonant inverter a DC voltage, with the value controlled from the power supply provided by the electrical system of the utility, and correct the power factor of the system as a whole. This level of DC bus voltage at the output of the first stage will be used to control the power transferred by the inverter to the load, and it may vary from 550 VDC to a maximum of 800 VDC. To control the voltage level of DC bus driver used a proportional integral (PI) controller and to achieve the unity power factor it was used two other proportional integral currents controllers. Computational simulations were performed to assist in sizing and forecasting performance. All the control and communications needed to stage supervisory were implemented on a DSP

Single-phase high power-factor boost ZCS pre-regulator operating in critical conduction mode

This paper presents a new single-phase interleaved high power factor boost pre-regulator operating in critical conduction mode, where the switches and boost diode performing zero-current commutations during its turn-off, eliminating the disadvantages related to the reverse recovery losses and electromagnetic interference problems of the boost diode, when operating in the continuous conduction mode. The interleaving technique is applied in the power cell, providing a significant input current ripple reduction in comparison to discontinuous mode of operation, due to its input current continuous conduction operation. This paper presents a complete modeling for the converter operating in critical conduction mode, resulting in an improved design procedure for interleaved techniques with high input power factor, a complete design procedure, and main simulation results from a design example with two interleaved cells rated at 1kW, 400V output voltage and 220V rms input voltage.

A thin layer electrochemical cell for disinfection of water contaminated with Staphylococcus aureus

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Resistive-Switching Behavior in Polycrystalline CaCu3Ti4O12 Nanorods

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Band-edge states of the zero(th)-order gap in quasi-periodic photonic superlattices

The photonic modes of Thue-Morse and Fibonacci lattices with generating layers A and B, of positive and negative indices of refraction, are calculated by the transfer-matrix technique. For Thue-Morse lattices, as well for periodic lattices with AB unit cell, the constructive interference of reflected waves, corresponding to the zero(th)-order gap, takes place when the optical paths in single layers A and B are commensurate. In contrast, for Fibonacci lattices of high order, the same phenomenon occurs when the ratio of those optical paths is close to the golden ratio. In the long wavelength limit, analytical expressions defining the edge frequencies of the zero(th) order gap are obtained for both quasi-periodic lattices. Furthermore, analytical expressions that define the gap edges around the zero(th) order gap are shown to correspond to the = 0 and = 0 conditions.

On the equivalence of the mechanisms governing switching and hysteresis phenomena

The nucleation and growth model, which is usually applied to switching phenomena, is adapted for explaining surface potential measurements on the P(VDF-TrFE) (polyvinylidene fluoride-trifluoroethylene) copolymer obtained in a constant current corona triode. It is shown that the growth is one-dimensional and that the nucleation rate is unimportant, probably because surface potential measurements take much longer than the switching ones. The surface potential data can therefore be accounted for by a growth model in which the velocity of growth varies exponentially with the electric field. Since hysteresis loops can be obtained from surface potential measurements, it is suggested that similar mechanisms can be used when treating switching and hysteresis phenomena, provided that account is taken of the difference in the time scale of the measurements.

Minimization of lead and copper interferences on spectrophotometric determination of cadmium using electrolytic deposition and ion-exchange in multi-commutation flow system

A new strategy for minimization of Cu2+ and Pb2+ interferences on the spectrophotometric determination of Cd2+ by the Malachite green (MG)-iodide reaction using electrolytic deposition of interfering species and solid phase extraction of Cd2+ in flow system is proposed. The electrolytic cell comprises two coiled Pt electrodes concentrically assembled. When the sample solution is electrolyzed in a mixed solution containing 5% (v/v) HNO3, 0.1% (v/v) H2SO4 and 0.5 M NaCl, Cu2+ is deposited as Cu on the cathode, Pb2+ is deposited as PbO2 on the anode while Cd2+ is kept in solution. After electrolysis, the remaining solution passes through an AG1-X8 resin (chloride form) packed minicolumn in which Cd2+ is extracted as CdCl4/2-. Electrolyte compositions, flow rates, timing, applied current, and electrolysis time was investigated. With 60 s electrolysis time, 0.25 A applied current, Pb2+ and Cu2+ levels up to 50 and 250 mg 1-1, respectively, can be tolerated without interference. For 90 s resin loading time, a linear relationship between absorbance and analyte concentration in the 5.00-50.0 μg Cd 1-1 range (r2 = 0.9996) is obtained. A throughput of 20 samples per h is achieved, corresponding to about 0.7 mg MG and 500 mg KI and 5 ml sample consumed per determination. The detection limit is 0.23 μg Cd 1-1. The accuracy was checked for cadmium determination in standard reference materials, vegetables and tap water. Results were in agreement with certified values of standard reference materials and with those obtained by graphite furnace atomic absorption spectrometry at 95% confidence level. The R.S.D. for plant digests and water containing 13.0 μg Cd 1-1 was 3.85% (n = 12). The recoveries of analyte spikes added to the water and vegetable samples ranged from 94 to 104%. (C) 2000 Elsevier Science B.V.

Electrode poling of cellular polypropylene films with short high-voltage pulses

Recently, piezoelectric cellular polypropylene (PP) was proposed as a new type of quasi-ferroelectric. The observed hysteresis of the charge density as a function of the electric field could be explained as field-dependent charging inside the gas-filled voids. Interestingly enough, the measurable poling behavior of the macroscopic dipoles formed by charges that are trapped at the internal void surfaces is phenomenologically completely identical to the cooperative poling behavior of microscopic molecular dipoles in ferroelectric polymers. Therefore, it can be assumed that charge separation (or charge redistribution) and subsequent trapping in cellular PP is a rather fast switching process. In order to examine the poling dynamics, we developed an experimental setup for pulsed poling. High-voltage pulses with a duration of 45 μs (FWHM) were applied in direct contact to two-side metallized cellular PP films. The pulsed poling yields piezoelectricity in the cellular PP. We study and discuss the dependence of the resulting piezoelectricity on the poling field. We also characterize the charge separation during application of higher electric poling fields of up to -10 kV in direct contact to the two-side metallized films for longer times.

An active leakage-injection scheme applied to low-voltage SRAMs

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

Resonant (P+RES) controller applied to voltage source inverter with minimum DC link capacitor

Voltage source inverters use large electrolytic capacitors in order to decouple the energy between the utility and the load, keeping the DC link voltage constant. Decreasing the capacitance reduces the distortion in the inverter input current but this also affects the load with low-order harmonics and generate disturbances at the input voltage. This paper applies the P+RES controller to solve the challenge of regulating the output current by means of controlling the magnitude of the current space vector, keeping it constant thus rejecting harmonic disturbances that would otherwise propagate to the load. This work presents a discussion of the switching and control strategy. © 2011 IEEE.

Experimental evaluation of the bridgeless interleaved boost PFC converter

This paper presents theoretical evaluation and experimental results to the proposed bridgeless interleaved boost PFC (power factor correction) converter. The application of bridgeless technique causes reduction of conduction losses, while the interleaving technique of the converter cells allows division of the current stress in semiconductor devices and reduction of weight and volume of the input EMI filter. In each cell of the converter, the inductor current operates in discontinuous conduction mode (DCM), which eliminates turn-on switching losses and the effects of reverse recovery in semiconductors, increasing the efficiency of the converter. The experimental results show the power factor of 0.96 for employed voltage ratio and an efficiency of 95.2 % for nominal load conditions. © 2012 IEEE.