264 resultados para WAFERS


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Si1-xGex/Si optoelectronic devices are promising for the monolithic integration with silicon-based microelectronics. SiGe/Si MQW RCE-PD (Resonant-Cavity-Enhanced photodiodes) with different structures were investigated in this work. Design and fabrication of top- and bottom-incident RCE-PD, such as growth of SiGe MQW (Multiple Quantum Wells) on Si and SOI (Si on insulator) wafers, bonding between SiGe epitaxial wafer and SOR (Surface Optical Reflector) consisting Of SiO2/Si DBR (Distributed Bragg Reflector) films on Si, and performances of RCE-PD, were presented. The responsivity of 44mA/W at 1.314 mum and the FWHM of 6nm were obtained at bias of 10V. The highest external quantum efficiency measured in the investigation is 4.2%.

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Silicon carbide (SiC) is recently receiving increased attention due to its unique electrical and thermal properties. It has been regarded as the most appropriate semiconductor material for high power, high frequency, high temperature, and radiation hard microelectronic devices. The fabrication processes and characterization of basic device on 6H-SiC were systematically studied. The main works are summarized as follows:The homoepitaxial growth on the commercially available single-crystal 6H-SiC wafers was performed in a modified gas source molecular beam epitaxy system. The mesa structured p(+)n junction diodes on the material were fabricated and characterized. The diodes showed a high breakdown voltage of 800 V at room temperature. They operated with good rectification characteristics from room temperature to 673 K.Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes were fabricated. They showed good rectification characteristics from room temperature to 473 K. Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800 V.n-Type 6H-SiC MOS capacitors were fabricated and characterized. Under the same growing conditions, the quality of polysilicon gate capacitors was better than Al. In addition, SiC MOS capacitors had good tolerance to gamma rays. (C) 2002 Published by Elsevier Science B.V.

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Low noise field effect transistors and analogue switch integrated circuits (ICs) have been fabricated in semi-insulating gallium arsenide (SI-GaAs) wafers grown in space by direct ion-implantation. The electrical behaviors of the devices and the ICs have surpassed those fabricated in the terrestrially grown SI-GaAs wafers. The highest gain and the lowest noise of the transistors made from space-grown SI-GaAs wafers are 22.8 dB and 0.78 dB, respectively. The threshold back-gating voltage of the ICs made from space-grown SI-GaAs wafers is better than 8.5 V The con-elation between the characterizations of materials and devices is studied systematically. (C) 2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

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A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

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Test strip detectors of 125 mu m, 500 mu m, and 1 mm pitches with about 1 cm(2) areas have been made on medium-resistivity silicon wafers (1.3 and 2.7 k Ohm cm). Detectors of 500 mu m pitch have been tested for charge collection and position precision before and after neutron irradiation (up to 2 x 10(14) n/cm(2)) using 820 and 1030 nm laser lights with different beam-spot sizes. It has been found that for a bias of 250 V a strip detector made of 1.3 k Ohm cm (300 mu m thick) can be fully depleted before and after an irradiation of 2 x 10(14) n/cm(2). For a 500 mu m pitch strip detector made of 2.7 k Ohm cm tested with an 1030 nm laser light with 200 mu m spot size, the position reconstruction error is about 14 mu m before irradiation, and 17 mu m after about 1.7 x 10(13) n/cm(2) irradiation. We demonstrated in this work that medium resistivity silicon strip detectors can work just as well as the traditional high-resistivity ones, but with higher radiation tolerance. We also tested charge sharing and position reconstruction using a 1030 nm wavelength (300 mu m absorption length in Si at RT) laser, which provides a simulation of MIP particles in high-physics experiments in terms of charge collection and position reconstruction, (C) 1999 Elsevier Science B.V. All rights reserved.

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A novel method is reported for the detection of avian influenza virus subtype H5 using a biosensor based on high spatial resolution imaging ellipsometry (IE). Monoclonal antibodies specific to H5 hemagglutinin protein were immobilized on silicon wafers and used to capture virus particles. Resultant changes on the surface of the wafers were visualized directly in gray-scale on an imaging ellipsometry image. This preliminary study has shown that the assay is rapid and specific for the identification of avian influenza virus subtype H5. Compared with lateral-flow immunoassays, this biosensor not only has better sensitivity, but can also simultaneously perform multiplexed tests. These results suggest that this biosensor might be a valuable diagnostic toot for avian influenza virus detection. (c) 2009 Elsevier B.V. All rights reserved.

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The fabrication and performance evaluation of a miniature twin-fuel-cell on silicon wafers are presented in this paper. The miniature twin-fuel-cell was fabricated in series using two membrane-electrode-assemblies sandwiched between two silicon substrates in which electric current, reactant, and product flow. The novel structure of the miniature twin-fuel-cell is that the electricity interconnect from the cathode of one cell to the anode of another cell is made on the same plane. The interconnect was fabricated by sputtering a layer of copper over a layer of gold on the top of the silicon wafer. Silicon dioxide was deposited on the silicon wafer adjacent to the copper layer to prevent short-circuiting between the twin cells. The feed holes and channels in the silicon wafers were prepared by anisotropic silicon etching from the back and front of the wafer with silicon dioxide acting as intrinsic etch-stop layer. Operating on dry H-2/O-2 at 25 degreesC and atmospheric pressure, the measured peak power density was 190.4 mW/cm(2) at 270 mA/cm(2) for the miniature twin-fuel-cell using a Nafion 112 membrane. Based on the polarization curves of the twin-fuel-cell and the two single cells, the interconnect resistance between the twin cells was calculated to be in the range from 0.0113 Omega (at 10 mA/cm(2)) to 0.0150 Omega (at 300 mA/cm(2)), which is relatively low. (C) 2003 Elsevier Science Ltd. All rights reserved.

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In this paper, the authors have systematically studied the microphase separation and crystallization during spin coating of an ABC triblock copolymer, polystyrene-b-poly(2-vinylpyridine)-b-poly(ethylene oxide) (PS-b-P2VP-b-PEO). The microphase separation of PS-b-P2VP-b-PEO and the crystallization of PEO blocks can be modulated by the types of the solvent and the substrate, the spinning speed, and the copolymer concentration. Ordered microphase-separated pattern, where PEO and P2VP blocks adsorbed to the substrate and PS blocks protrusions formed hexagonal dots above the P2VP domains, can only be obtained when PS-b-P2VP-b-PEO is dissolved in N,N-dimethylformamide and the films are spin coated onto the polar substrate, silicon wafers or mica. The mechanism of the formation of regular pattern by microphase separation is found to be mainly related to the inducement of the substrate (middle block P2VP wetting the polar substrate), the quick vanishment of the solvent during the early stage of the spin coating, and the slow evaporation of the remaining solvent during the subsequent stage. On the other hand, the probability of the crystallization of PEO blocks during spin coating decreases with the reduced film thickness. When the film thickness reaches a certain value (3.0 nm), the extensive crystallization of PEO is effectively prohibited and ordered microphase-separated pattern over large areas can be routinely prepared.

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The thin films of poly(methyl methacrylate) (PMMA), poly(styrene-co-acrylonitrile) (SAN) and their blends were prepared by means of spin-coating their corresponding solutions onto silicon wafers, followed by being annealed at different temperatures. The surface phase separations of PMMA/SAN blends were characterized by virtue of atomic force microscopy (AFM). By comparing the tapping mode AFM (TM-AFM) phase images of the pure components and their blends, surface phase separation mechanisms of the blends could be identified as the nucleation and growth mechanism or the spinodal decomposition mechanism. Therefore, the phase diagram of the PMMA/SAN system could be obtained by means of TM-AFM. Contact mode AFM was also used to study the surface morphologies of all the samples and the phase separations of the blends occurred by the spinodal decomposition mechanism could be ascertained. Moreover, X-ray photoelectron spectroscopy was used to characterize the chemical compositions on the surfaces of the samples and the miscibility principle of the PMMA/SAN system was discussed.

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Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

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Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

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Solar Energy is a clean and abundant energy source that can help reduce reliance on fossil fuels around which questions still persist about their contribution to climate and long-term availability. Monolithic triple-junction solar cells are currently the state of the art photovoltaic devices with champion cell efficiencies exceeding 40%, but their ultimate efficiency is restricted by the current-matching constraint of series-connected cells. The objective of this thesis was to investigate the use of solar cells with lattice constants equal to InP in order to reduce the constraint of current matching in multi-junction solar cells. This was addressed by two approaches: Firstly, the formation of mechanically stacked solar cells (MSSC) was investigated through the addition of separate connections to individual cells that make up a multi-junction device. An electrical and optical modelling approach identified separately connected InGaAs bottom cells stacked under dual-junction GaAs based top cells as a route to high efficiency. An InGaAs solar cell was fabricated on an InP substrate with a measured 1-Sun conversion efficiency of 9.3%. A comparative study of adhesives found benzocyclobutene to be the most suitable for bonding component cells in a mechanically stacked configuration owing to its higher thermal conductivity and refractive index when compared to other candidate adhesives. A flip-chip process was developed to bond single-junction GaAs and InGaAs cells with a measured 4-terminal MSSC efficiency of 25.2% under 1-Sun conditions. Additionally, a novel InAlAs solar cell was identified, which can be used to provide an alternative to the well established GaAs solar cell. As wide bandgap InAlAs solar cells have not been extensively investigated for use in photovoltaics, single-junction cells were fabricated and their properties relevant to PV operation analysed. Minority carrier diffusion lengths in the micrometre range were extracted, confirming InAlAs as a suitable material for use in III-V solar cells, and a 1-Sun conversion efficiency of 6.6% measured for cells with 800 nm thick absorber layers. Given the cost and small diameter of commercially available InP wafers, InGaAs and InAlAs solar cells were fabricated on alternative substrates, namely GaAs. As a first demonstration the lattice constant of a GaAs substrate was graded to InP using an InxGa1-xAs metamorphic buffer layer onto which cells were grown. This was the first demonstration of an InAlAs solar cell on an alternative substrate and an initial step towards fabricating these cells on Si. The results presented offer a route to developing multi-junction solar cell devices based on the InP lattice parameter, thus extending the range of available bandgaps for high efficiency cells.

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Surface plasmons supported by metal nanoparticles are perturbed by coupling to a surface that is polarizable. Coupling results in enhancement of near fields and may increase the scattering efficiency of radiative modes. In this study, we investigate the Rayleigh and Raman scattering properties of gold nanoparticles functionalized with cyanine deposited on silicon and quartz wafers and on gold thin films. Dark-field scattering images display red shifting of the gold nanoparticle plasmon resonance and doughnut-shaped scattering patterns when particles are deposited on silicon or on a gold film. The imaged radiation patterns and individual particle spectra reveal that the polarizable substrates control both the orientation and brightness of the radiative modes. Comparison with simulation indicates that, in a particle-surface system with a fixed junction width, plasmon band shifts are controlled quantitatively by the permittivity of the wafer or the film. Surface-enhanced resonance Raman scattering (SERRS) spectra and images are collected from cyanine on particles on gold films. SERRS images of the particles on gold films are doughnut-shaped as are their Rayleigh images, indicating that the SERRS is controlled by the polarization of plasmons in the antenna nanostructures. Near-field enhancement and radiative efficiency of the antenna are sufficient to enable Raman scattering cyanines to function as gap field probes. Through collective interpretation of individual particle Rayleigh spectra and spectral simulations, the geometric basis for small observed variations in the wavelength and intensity of plasmon resonant scattering from individual antenna on the three surfaces is explained.

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Spatially resolved measurements of the atomic oxygen densities close to a sample surface in a dual mode (capacitive/inductive) rf plasma are used to measure the atomic oxygen surface loss coefficient beta on stainless steel and aluminum substrates, silicon and silicon dioxide wafers, and on polypropylene samples. beta is found to be particularly sensitive to the gas pressure for both operating modes. It is concluded that this is due to the effect of changing atom and ion flux to the surface. (C) 2002 American Institute of Physics.

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Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.