The ZVS-PWM commutation cell applied to the DC-AC converter

This paper presents the analysis of a dc-ac converter using a zero-voltage-switching (ZVS) commutation cell. First, we show the cell applied to the buck converter. The stages of operation are presented along with the main current and voltage equations. Next, we adapt the converter to the regenerative-operation mode. Hence, the full-bridge converter at low-frequency operation is connected in the dc-dc output stage (at high frequency). The main switches commute at zero voltage. The converter operated at constant frequency with pulse-width modulation (PWM), and neither overvoltage nor additional current stress was observed by digital simulation. A design example and experimental results obtained by prototype, rated at 275 V and 1 kW, are also presented. © 1997 IEEE.

A HPF AC-AC converter for Permanent Magnet Generator applications

This paper describes the design and development of a high input power-factor (HPF) AC to AC converter for naval applications using Permanent Magnet Generator (PMG). The proposed converter comprises an isolated three-phase uncontrolled multipulse rectification stage directly connected to a single-phase inverter stage, without the use of DC to DC intermediary stage, resulting in more simplicity for the overall circuitry, assuring robustness, reliability and reduced costs. Furthermore, the multipulse rectifier stage is capable to provide high power factor and input currents with low total harmonic distortion (THD). The output voltage of the PMG varies from 260V rms (220 Hz) to 380V rms (360 Hz), depending on load conditions. The output single-phase inverter stage was designed to operate with wide range of DC bus voltage, maintaining 120V rms, 60 Hz output. Measured total harmonic distortion for the AC output voltage represents less than 2%, at 3.6kW nominal linear load. © 2010 IEEE.

Hybrid model of a double-fed induction machine and back-to-back converter

This report details the port interconnection of two subsystems: a power electronics subsystem (a back-to-back AC/AC converter (B2B), coupled to a phase of the power grid), and an electromechanical subsystem (a doubly-fed induction machine (DFIM), coupled mechanically to a flywheel and electrically to the power grid and to a local varying load). Both subsystems have been essentially described in previous reports (deliverables D 0.5 and D 4.3.1), although some previously unpublished details are presented here. The B2B is a variable structure system (VSS), due to the presence of control-actuated switches: however from a modelling and simulation, as well as a control-design, point of view, it is sensible to consider modulated transformers (MTF in the bond-graph language) instead of the pairs of complementary switches. The port-Hamiltonian models of both subsystems are presents and coupled through a power-preserving interconnection, and the Hamiltonian description of the whole system is obtained; detailed bond-graphs of all the subsystems and the complete system are provided.

Energy-based modelling and simulation of the interconnection of a back-to-back converter and a doubly-fed induction machine

This paper describes the port interconnection of two subsystems: a power electronics subsystem (a back-to-back AC/CA converter (B2B), coupled to a phase of the power grid), and an electromechanical subsystem (a doubly-fed induction machine (DFIM). The B2B is a variable structure system (VSS), due to presence of control-actuated switches: however, from a modelling simulation, as well as a control-design, point of view, it is sensible to consider modulated transformers (MTF in the bond graph language) instead of the pairs of complementary switches. The port-Hamiltonian models of both subsystems are presented and, using a power-preserving interconnection, the Hamiltonian description of the whole system is obtained; detailed bond graphs of all subsystems and the complete system are also provided. Using passivity-based controllers computed in the Hamiltonian formalism for both subsystems, the whole model is simulated; simulations are run to rest the correctness and efficiency of the Hamiltonian network modelling approach used in this work.

A novel Sigma–Delta based parallel analogue-to-residue converter

Animportant step in the residue number system(RNS) based signal processing is the conversion of signal into residue domain. Many implementations of this conversion have been proposed for various goals, and one of the implementations is by a direct conversion from an analogue input. A novel approach for analogue-to-residue conversion is proposed in this research using the most popular Sigma–Delta analogue-to-digital converter (SD-ADC). In this approach, the front end is the same as in traditional SD-ADC that uses Sigma–Delta (SD) modulator with appropriate dynamic range, but the filtering is doneby a filter implemented usingRNSarithmetic. Hence, the natural output of the filter is an RNS representation of the input signal. The resolution, conversion speed, hardware complexity and cost of implementation of the proposed SD based analogue-to-residue converter are compared with the existing analogue-to-residue converters based on Nyquist rate ADCs

Wind turbines equipped with fractional-order controllers: Stress on the mechanical drive train due to a converter control malfunction

This paper is on variable-speed wind turbines with permanent magnet synchronous generator (PMSG). Three different drive train mass models and three different topologies for the power-electronic converters are considered. The three different topologies considered are respectively a matrix, a two-level and a multilevel converter. A novel control strategy, based on fractional-order controllers, is proposed for the wind turbines. Simulation results are presented to illustrate the behaviour of the wind turbines during a converter control malfunction, considering the fractional-order controllers. Finally, conclusions are duly drawn. Copyright (C) 2010 John Wiley & Sons, Ltd.

ROM-less RNS-to-binary converter moduli {22N − 1, 22N + 1, 2N − 3, 2N + 3}

In this paper, a novel ROM-less RNS-to-binary converter is proposed, using a new balanced moduli set {22n-1, 22n + 1, 2n-3, 2n + 3} for n even. The proposed converter is implemented with a two stage ROM-less approach, which computes the value of X based only in arithmetic operations, without using lookup tables. Experimental results for 24 to 120 bits of Dynamic Range, show that the proposed converter structure allows a balanced system with 20% faster arithmetic channels regarding the related state of the art, while requiring similar area resources. This improvement in the channel's performance is enough to offset the higher conversion costs of the proposed converter. Furthermore, up to 20% better Power-Delay-Product efficiency metric can be achieved for the full RNS architecture using the proposed moduli set. © 2014 IEEE.

Arithmetic-based binary-to-RNS converter modulo {2(n)+/- k} for jn-Bit dynamic range

In this brief, a read-only-memoryless structure for binary-to-residue number system (RNS) conversion modulo {2(n) +/- k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing {2(n) +/- k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the {2(n) +/- k} moduli is performed.

SI SC MDAC switched current-capacitor multiplying digital-to-analog converter

Dissertação apresentada para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

A rule-based grapheme-to-phone converter for TTS systems in european portuguese

In this paper, a linguistically rule-based grapheme-to-phone (G2P) transcription algorithm is described for European Portuguese. A complete set of phonological and phonetic transcription rules regarding the European Portuguese standard variety is presented. This algorithm was implemented and tested by using online newspaper articles. The obtained experimental results gave rise to 98.80% of accuracy rate. Future developments in order to increase this value are foreseen. Our purpose with this work is to develop a module/ tool that can improve synthetic speech naturalness in European Portuguese. Other applications of this system can be expected like language teaching/learning. These results, together with our perspectives of future improvements, have proved the dramatic importance of linguistic knowledge on the development of Text-to-Speech systems (TTS).

Visualization Resources for Iowa State University and the Iowa DOT: An Automated Design Model to Simulator Converter, November 2012

This project developed an automatic conversion software tool that takes input a from an Iowa Department of Transportation (DOT) MicroStation three-dimensional (3D) design file and converts it into a form that can be used by the University of Iowa’s National Advanced Driving Simulator (NADS) MiniSim. Once imported into the simulator, the new roadway has the identical geometric design features as in the Iowa DOT design file. The base roadway appears as a wireframe in the simulator software. Through additional software tools, textures and shading can be applied to the roadway surface and surrounding terrain to produce the visual appearance of an actual road. This tool enables Iowa DOT engineers to work with the universities to create drivable versions of prospective roadway designs. By driving the designs in the simulator, problems can be identified early in the design process. The simulated drives can also be used for public outreach and human factors driving research.

Visualization Resources for Iowa State University and the Iowa DOT: An Automated Design Model to Simulator Converter, November 2012

The creation of three-dimensional (3D) drawings for proposed designs for construction, re-construction and rehabilitation activities are becoming increasingly common for highway designers, whether by department of transportation (DOT) employees or consulting engineers. However, technical challenges exist that prevent the use of these 3D drawings/models from being used as the basis of interactive simulation. Use of driving simulation to service the needs of the transportation industry in the US lags behind Europe due to several factors, including lack of technical infrastructure at DOTs, cost of maintaining and supporting simulation infrastructure—traditionally done by simulation domain experts—and cost and effort to translate DOT domain data into the simulation domain.

Visualization Resources for Iowa State University and the Iowa DOT: An Automated Design Model to Simulator Converter, November 2012

The creation of three-dimensional (3D) drawings for proposed designs for construction, re-construction and rehabilitation activities are becoming increasingly common for highway designers, whether by department of transportation (DOT) employees or consulting engineers. However, technical challenges exist that prevent the use of these 3D drawings/models from being used as the basis of interactive simulation. Use of driving simulation to service the needs of the transportation industry in the US lags behind Europe due to several factors, including lack of technical infrastructure at DOTs, cost of maintaining and supporting simulation infrastructure—traditionally done by simulation domain experts—and cost and effort to translate DOT domain data into the simulation domain.

An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.

Time to digital converter

In questa tesi è analizzato il caso di sensori con uscita in frequenza e periodo, si traduce in ultima analisi nella capacità di misurare con precisione un intervallo temporale. La rivelazione del tempo risulta essere lo stadio fondamentale da cui deriva la risoluzione dell'intero sistema di misura. Nella realtà, la questione della simultaneità cioè individuare con assoluta precisione due eventi che si verificano contemporaneamente, in un determinato istante t, è un problema piuttosto complesso: le difficoltà sono correlate soprattutto alle limitazioni fisiche intrinseche degli strumenti di misura. E' utile allora fornire un'analisi sui principi e le tecniche alla base della misura di intervalli temporali, detta Time Interval Measurement (TIM). Lo scopo della tesi è studiare i vari metodi per realizzare TDC lineari digitali, facendo un'analisi critica e ed evidenziando pro e contro che i vari approcci presentano, attingendo e analizzando criticamente informazioni dalle varie fonti riportate in bibliografia.