Magnetoresistance and transistor-like behavior of a double quantum-dot via crossed Andreev reflections

The electric current and the magnetoresistance effect are studied in a double quantum-dot system, where one of the dots QD(a) is coupled to two ferromagnetic electrodes (F-1; F-2), while the second QD(b) is connected to a superconductor S. For energy scales within the superconductor gap, electric conduction is allowed by Andreev reflection processes. Due to the presence of two ferromagnetic leads, non-local crossed Andreev reflections are possible. We found that the magnetoresistance sign can be changed by tuning the external potential applied to the ferromagnets. In addition, it is possible to control the current of the first ferromagnet (F-1) through the potential applied to the second one (F-2). We have also included intradot interaction and gate voltages at each quantum dot and analyzed their influence through a mean field approximation. The interaction reduces the current amplitudes with respect to the non-interacting case, but the switching effect still remains as a manifestation of quantum coherence, in scales of the order of the superconductor coherence length. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4723000]

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

Al2O3 obtained through resistive evaporation for use as insulating layer in transparent field effect transistor

Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O-2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550 degrees C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.

Al2O3 Obtained through resistive evaporation for use as insulating layer in transparent field effect transistor

Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550°C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.

Separating interface state response from parasitic effects in conductance measurements on organic metal-insulator-semiconductor capacitors

A simple model is developed for the admittance of a metal-insulator-semiconductor (MIS) capacitor which includes the effect of a guard ring surrounding the Ohmic contact to the semiconductor. The model predicts most of the features observed in a MIS capacitor fabricated using regioregular poly(3-hexylthiophene) as the active semiconductor and polysilsesquioxane as the gate insulator. In particular, it shows that when the capacitor is driven into accumulation, the parasitic transistor formed by the guard ring and Ohmic contact can give rise to an additional feature in the admittance-voltage plot that could be mistaken for interface states. When this artifact and underlying losses in the bulk semiconductor are accounted for, the remaining experimental feature, a peak in the loss-voltage plot when the capacitor is in depletion, is identified as an interface (or near interface) state of density of similar to 4 x 10(10) cm(-2) eV(-1). Application of the model shows that exposure of a vacuum-annealed device to laboratory air produces a rapid change in the doping density in the channel region of the parasitic transistor but only slow changes in the bulk semiconductor covered by the gold Ohmic contact. (C) 2008 American Institute of Physics.

Winner-take-all circuit using CMOS technology

In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).

Novel high-power-factor ZCS-PWM preregulators

This paper introduces novel zero-current-switching (ZCS) pulsewidth-modulated (PWM) preregulators based on a new soft-commutation cell, suitable for insulated gate bipolar transistor applications. The active switches in these proposed rectifiers turn on in zero current and turn off in zero current-zero voltage. In addition, the diodes turn on in zero voltage and their reverse-recovery effects over the active switches are negligible. Moreover, based on the proposed cell, an entire family of de-to-de ZCS-PWM converters can be generated, providing conditions to obtain naturally isolated converters, for example, derived buck-boost, Sepic. and Zeta converters. The novel ac-to-dc ZCS-PWM boost and Zeta preregulators are presented in order to verify the operation of this soft-commutation cell, In order to minimize the harmonic contents of the input current, increasing the ac power factor, the average-current-mode control is used, obtaining preregulators with ac power factor near unity and high efficiency at wide load range. The principle of operation, theoretical analysis, design example, and experimental results from test units for the novel preregulators are presented. The new boost preregulator was designed to nominal values of 1.6 kW output power, 220 V(rms) input voltage, 400 V(dc) output voltage, and operating at 20 kHz. The measured efficiency and power factor of the new ZCS-PWM boost preregulator were 96.7% and 0,99, respectively, with an input current total harmonic distortion (THD) equal to 3.42% for an input voltage with THD equal to 1.61%, at rated load, the new ZCS-PWM Zeta preregulator was designed to voltage step-down operation, and the experimental results were obtained from a laboratory prototype rated at 500 W, 220 V(rm), input voltage, 110 V(dc) output voltage, and operating at 50 kHz. The measured efficiency of the new ZCS-PWM Zeta preregulator is approximately 96.9% and the input power factor is 0.98, with an input current THD equal to 19.07% while the input voltage THD is equal to 1.96%, at rated load.

A tunable triode-MOSFET transconductor and its application to g(m)-C filters

A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.

Settling analysis of MOS regulated current mirrors applied to micropower D/A converters

This paper provides an insight to the trade-off between settling time and power consumption in regulated current mirrors as building parts in micropower current-switching D/A converters. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are evaluated. Raising pole frequencies in micropower circuits, while meeting consumption requirements, is basically limited by parasitic capacitances. For such cases, an alternative is to impose a twin-pole condition in which design constraints are somewhat relieved and settling slightly improved. Relationships between pole frequencies, transistor geometry and bias are established and design guidelines for regulated current mirrors founded. By placing loop-transistors in either weak or strong inversion, small (W/L) ratios are allowed and stray capacitances reduced. Simulated waveforms suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves both simulated and experimental settling performance.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

A configurable approach to circuit simulation

This paper presents a configurable architecture which was designed to aid in the simulation of ULSI circuits at the transistor level. Elsewhere [1] this architecture was shown to be able to run such simulations several times as fast as standard circuit simulators such as SPICES. In this paper, after describing the overall idea and the the architecture of the system as a whole, I concentrate on the description of the architecture of the processing elements of the computing array.

On optimizing micropower MOS regulated cascode circuits on switched current techniques

Trade-off between settling time and micropower consumption in MOS regulated cascode current sources as building parts in high-accuracy, current-switching D/A converters is analyzed. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are discussed. Raising pole frequencies while meeting consumption requirements is basically limited by parasitic capacitances. An alternative is found by imposing a twin-pole system in which design constraints are somewhat relaxed and settling slightly faster. Relationships between pole frequencies, transistor geometry and bias are established. Simulated waveforms obtained with PSpice of designed circuits following a voltage perturbation suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves its simulated settling performance.

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

Thermoelectric effects in quantum dots

We report a numerical renormalization-group study of the thermoelectric effect in the single-electron transistor (SET) and side-coupled geometries. As expected, the computed thermal conductance and thermopower curves show signatures of the Kondo effect and of Fano interference. The thermopower curves are also affected by particle-hole asymmetry. © 2009 Elsevier B.V. All rights reserved.