A configurable approach to circuit simulation
| Contribuinte(s) |
Universidade Estadual Paulista (UNESP) |
|---|---|
| Data(s) |
20/05/2014
20/05/2014
01/01/2000
|
| Resumo |
This paper presents a configurable architecture which was designed to aid in the simulation of ULSI circuits at the transistor level. Elsewhere [1] this architecture was shown to be able to run such simulations several times as fast as standard circuit simulators such as SPICES. In this paper, after describing the overall idea and the the architecture of the system as a whole, I concentrate on the description of the architecture of the processing elements of the computing array. |
| Formato |
1539-1544 |
| Identificador |
http://www.dcce.ibilce.unesp.br/~norian/publicacoes/pdpta2000.pdf Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v. Athens: C S R E A Press, p. 1539-1544, 2000. http://hdl.handle.net/11449/39510 WOS:000167676300211 |
| Idioma(s) |
eng |
| Publicador |
C S R E A Press |
| Relação |
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v |
| Direitos |
openAccess |
| Tipo |
info:eu-repo/semantics/conferencePaper |
