Towards a java bytecodes compiler for nios II soft-core processor

Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.

Exploiting Distinct Molecular Architectures of Ultrathin Films Made with Iron Phthalocyanine for Sensing

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Modeling of optoelectronic devices through neuro-fuzzy architectures

The advantages offered by the electronic component LED (Light Emitting Diode) have caused a quick and wide application of this device in replacement of incandescent lights. However, in its combined application, the relationship between the design variables and the desired effect or result is very complex and it becomes difficult to model by conventional techniques. This work consists of the development of a technique, through comparative analysis of neuro-fuzzy architectures, to make possible to obtain the luminous intensity values of brake lights using LEDs from design data.

Efficient microwave-assisted hydrothermal synthesis of CuO sea urchin-like architectures via a mesoscale self-assembly

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

ZnO architectures synthesized by a microwave-assisted hydrothermal method and their photoluminescence properties

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Design of a simplified neuro-fuzzy system based on CMAC Architectures

This work presents the design of a fuzzy controller with simplified architecture that use an artificial neural network working as the aggregation operator for several active fuzzy rules. The simplified architecture of the fuzzy controller is used to minimize the time processing used in the closed loop system operation, the basic procedures of fuzzification are simplified to maximum while all the inference procedures are computed in a private way. As consequence, this simplified architecture allows a fast and easy configuration of the simplified fuzzy controller. The structuring of the fuzzy rules that define the control actions is previously computed using an artificial neural network based on CMAC Cerebellar Model Articulation Controller. The operational limits are standardized and all the control actions are previously calculated and stored in memory. For applications, results and conclusions several configurations of this fuzzy controller are considered.

A simple mechanism to deal with sequential code in dataflow architectures

The aim of this work is to propose a simple and efficient mechanism to deal with the problem of executing sequential code in a pure dataflow machine. Our results is obtained with a simulator of Wolf [4] architecture. The implemented mechanism improved the architecture performance when executing sequential code and we expect that this improvement could be better if we use some heuristics to deal with some special groups of instructions such as branch operations. Further research will show us if this is true.

Dressing monitoring with a digital signal processor

Grinding is a finishing process in machining operations, and the topology of the grinding tool is responsible for producing the desired result on the surface of the machined material The tool topology is modeled in the dressing process and precision is therefore extremely important This study presents a solution in the monitoring of the dressing process, using a digital signal processor (DSP) operating in real time to detect the optimal dressing moment To confirm the monitoring efficiency by DSP, the results were compared with those of a data acquisition system (DAQ) and offline processing The method employed here consisted of analyzing the acoustic emission and electrical power signal by applying the DPO and DPKS parameters The analysis of the results allowed us to conclude that the application of the DPO and DPKS parameters can be substituted by processing of the mean acoustic emission signal, thus reducing the computational effort

Noise reduction in speech signals using a TMS320C31 digital signal processor

This paper describes a speech enhancement system (SES) based on a TMS320C31 digital signal processor (DSP) for real-time application. The SES algorithm is based on a modified spectral subtraction method and a new speech activity detector (SAD) is used. The system presents a medium computational load and a sampling rate up to 18 kHz can be used. The goal is load and a sampling rate up to 18 kHz can be used. The goal is to use it to reduce noise in an analog telephone line.

Network node with wireless and wired interfaces: Nios II processor and uClinux to development of a NCAP embedded (IEEE 1451.1) with two interfaces, wireless (IEEE 1451.5) and wired (IEEE p1451.2)

This paper presents a NCAP embedded on DE2 kit with Nios II processor and uClinux to development of a network gateway with two interfaces, wireless (ZigBee) and wired (RS232) based on IEEE 1451. Both the communications, wireless and wired, were developed to be point-to-point and working with the same protocols, based on IEEE 1451.0-2007. The tests were made using a microcomputer, which through of browser was possible access the web page stored in the DE2 kit and send commands of control and monitoring to both TIMs (WTIM and STIM). The system describes a different form of development of the NCAP node to be applied in different environments with wired or wireless in the same node. © 2011 IEEE.

Energy-performance tradeoffs in software transactional memory

Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.

Compilação para arquitetura reconfigurável

Pós-graduação em Ciência da Computação - IBILCE

Análise e síntese de um processador digital wavelet

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Comparing label free electrochemical impedimetric and capacitive biosensing architectures

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)