Towards a java bytecodes compiler for nios II soft-core processor


Autoria(s): Lima, Willian S.; Lobato, Renata S.; Manacero, Aleardo; Spolon, Roberta
Contribuinte(s)

Universidade Estadual Paulista (UNESP)

Data(s)

27/05/2014

27/05/2014

19/11/2009

Resumo

Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.

Formato

104-109

Identificador

http://dx.doi.org/10.1109/ISCC.2009.5202253

Proceedings - IEEE Symposium on Computers and Communications, p. 104-109.

1530-1346

http://hdl.handle.net/11449/71241

10.1109/ISCC.2009.5202253

WOS:000277119300017

2-s2.0-70449513605

Idioma(s)

eng

Relação

Proceedings - IEEE Symposium on Computers and Communications

Direitos

closedAccess

Palavras-Chave #Bytecodes #Control flows #Dependence graphs #Instruction set #Java bytecodes #NIOS II #Reconfigurable architecture #Reconfigurable computing #Reconfigurable devices #Research topics #Soft-core processors #Source codes #Building codes #Computer architecture #High level languages #Program compilers
Tipo

info:eu-repo/semantics/conferencePaper