Development of a varactor -controlled dual-frequency reconfigurable microstrip antenna

A new design for a compact electronically reconffgurable singlefeed dual frequency dual-polarized operation of a square-microstrip antenna capable of achieving tunable frequency ratios in the range 1.1 to 1.37 is proposed and experimentally studied. Varactor diodes inlegruted with the arms of the hexagonal slot and embedded in the square patch are used to tune the operating frequencies by applying reverse-bias voltage. The design has the advantage of size reduction up to 73.21% and 49.86% for the two resonant frequencies, respectively, as compared to standard rectangular patches. The antenna offers good bandwidth of 5.74% and 5.36% for the two operating frequencies. A highly simplified tuning circuitry without any transmission lines adds to the compactness of the design

A Compact Electronically Reconfigurable Dual Frequency Microstrip Antenna for L-Band Applications

A novel design of a computer electronically reconfigurable dual frequency dual polarized single feed hexagonal slot loaded microstrip antenna in L-band is introduced in this chapter. pin diodes are used to switch the operating frequencies considerably without much affecting the radiation characteristics and gain. the antenna can work with a frequency ratio varying in the wide range from 1.2 to 1.4. the proposed design has an added advantage of size reduction up to 72.21% and 46.84% for the two resonating frequencies compared to standard rectangular patches. the design also gives considerable bandwidth of up to 2.82% and 2.42 % for the operating frequencies.

Realization of Optical Logic Gates Using the Thermal Lens Effect

A sensitive method based on the principle of photothermal phenomena to realize optical logic gates is presented. A dual beam thermal lens method using low power cw lasers in a dye-doped polymer can be very effectively used as an alternate technique to perform the logical function such as NAND, AND and OR.

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Design of Compact Reconfigurable Dual Frequency Microstrip Antennas Using Varactor Diodes

The design of a compact, single feed, dual frequency dual polarized and electronically reconfigurable microstrip antenna is presented in this paper. A square patch loaded with a hexagonal slot having extended slot arms constitutes the fundamental structure of the antenna. The tuning of the two resonant frequencies is realized by varying the effective electrical length of the slot arms by embedding varactor diodes across the slots. A high tuning range of 34.43% (1.037–1.394 GHz) and 9.27% (1.359–1.485 GHz) is achieved for the two operating frequencies respectively, when the bias voltage is varied from 0 to −30 V. The salient feature of this design is that it uses no matching networks even though the resonant frequencies are tuned in a wide range with good matching below −10 dB. The antenna has an added advantage of size reduction up to 80.11% and 65.69% for the two operating frequencies compared to conventional rectangular patches.

C-shaped slot loaded reconfigurable microstrip antenna

A new electronically reconfigurable dual frequency microstrip patch antenna with highly simplified varactor tuning circuitry is presented. The proposed design allows relatively independent selection of the two operating frequencies. Tuning ranges of 7.1 and 4.1% are realised for the two resonant frequencies without the use of any matching circuits.

Investigations on Reconfigurable Dual Frequency Microstrip Antennas Controlled by PIN Diodes and Varactors

In this work,we investigate novel designs of compact electronically reconfigurable dual frequency microstrip antennas with a single feed,operating mainly in L-band,without using any matching networks and complicated biasing circuitry.These antennas have been designed to operate in very popular frequency range where a great number of wireless communication applications exist.Efforts were carried out to introduce a successful,low cost reconfigurable dual-frequency microstrip antenna design to the wireless and radio frequency design community.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.