Dynamic mechanical analysis of binary and ternary polymer blends based on nylon copolymer/EPDM rubber and EPM grafted maleic anhydride compatibilizer

The dynamic mechanical properties such as storage modulus, loss modulus and damping properties of blends of nylon copolymer (PA6,66) with ethylene propylene diene (EPDM) rubber was investigated with special reference to the effect of blend ratio and compatibilisation over a temperature range –100°C to 150°C at different frequencies. The effect of change in the composition of the polymer blends on tanδ was studied to understand the extent of polymer miscibility and damping characteristics. The loss tangent curve of the blends exhibited two transition peaks, corresponding to the glass transition temperature (Tg) of individual components indicating incompatibility of the blend systems. The morphology of the blends has been examined by using scanning electron microscopy. The Arrhenius relationship was used to calculate the activation energy for the glass transition of the blends. Finally, attempts have been made to compare the experimental data with theoretical models.

Studies on New Binary Accelerator Systems in Rubber Vulcanisation

Department of Polymer Science and Rubber Technology, Cochin University of Science and Technology

Acid-Base, Surface electron donating and catalytic properties of binary oxides of Zr with rare earth elements

Department of Applied Chemistry, Cochin University of Science and Technology

Acid base characteristics of binary oxides of Zr with Ce and La

The surface acidity and basicity of binary oxides of Zr with Ce and La are determined using a series of Hammet indicators and Ho,,max values are reported. The generation of new acid sites habe been ascribed to the charge imbalance of M1-O-M2 bonds, where M1 and M2 are metal atoms. Both Bronsted and Lewis acid sites contribute to the acidity of the oxides

Realization of Optical Logic Gates Using the Thermal Lens Effect

A sensitive method based on the principle of photothermal phenomena to realize optical logic gates is presented. A dual beam thermal lens method using low power cw lasers in a dye-doped polymer can be very effectively used as an alternate technique to perform the logical function such as NAND, AND and OR.

A Study of Morphological Operators with Applications

The present work deals with the A study of morphological opertors with applications. Morphology is now a.necessary tool for engineers involved with imaging applications. Morphological operations have been viewed as filters the properties of which have been well studied (Heijmans, 1994). Another well-known class of non-linear filters is the class of rank order filters (Pitas and Venetsanopoulos, 1990). Soft morphological filters are a combination of morphological and weighted rank order filters (Koskinen, et al., 1991, Kuosmanen and Astola, 1995). They have been introduced to improve the behaviour of traditional morphological filters in noisy environments. The idea was to slightly relax the typical morphological definitions in such a way that a degree of robustness is achieved, while most of the desirable properties of typical morphological operations are maintained. Soft morphological filters are less sensitive to additive noise and to small variations in object shape than typical morphological filters. They can remove positive and negative impulse noise, preserving at the same time small details in images. Currently, Mathematical Morphology allows processing images to enhance fuzzy areas, segment objects, detect edges and analyze structures. The techniques developed for binary images are a major step forward in the application of this theory to gray level images. One of these techniques is based on fuzzy logic and on the theory of fuzzy sets.Fuzzy sets have proved to be strongly advantageous when representing in accuracies, not only regarding the spatial localization of objects in an image but also the membership of a certain pixel to a given class. Such inaccuracies are inherent to real images either because of the presence of indefinite limits between the structures or objects to be segmented within the image due to noisy acquisitions or directly because they are inherent to the image formation methods.

Study on acceleratore in rubber vulcanization with special reference to the binary systems containing substituted dithiobiurets

The thesis entitled Study on Accelerators in Rubber Vulcanization with Special Reference to the Binary Systems Containing Substituted Dithiobiurets. It includes a detailed study on the binary accelerator systems containing substituted dithiobiurets in natural rubber and NR latex and dithiobiurets in SBR and NR-SBR blends vulcanization systems. It deals with the experimental procedure adopted for the preparation of DTB-II and DTB-III; the procedure for compounding and vulcanization and determination of physical properties like modulus, tensile strength, elongation at break, hardness, compression set, heat build up etc. The results indicate that there is efficient acceleration activity of the dithiobiurets in the vulcanization of natural rubber latex containing TMT. The study of dithiobiurets in natural rubber and NR latex reveal that they are having definite accelerating effect in SBR vulcanization systems.

Acid-Base. Surface Electron Donatin6 &.Catai.Ytlc Properties Of Some Binary Mixed Oxides Containing Rare Earth Elements

Catalysis research underpins the science of modern chemical processing and fuel technologies. Catalysis is commercially one of the most important technologies in national economies. Solid state heterogeneous catalyst materials such as metal oxides and metal particles on ceramic oxide substrates are most common. They are typically used with commodity gases and liquid reactants. Selective oxidation catalysts of hydrocarbon feedstocks is the dominant process of converting them to key industrial chemicals, polymers and energy sources.[1] In the absence of a unique successfiil theory of heterogeneous catalysis, attempts are being made to correlate catalytic activity with some specific properties of the solid surface. Such correlations help to narrow down the search for a good catalyst for a given reaction. The heterogeneous catalytic performance of material depends on many factors such as [2] Crystal and surface structure of the catalyst. Thermodynamic stability of the catalyst and the reactant. Acid- base properties of the solid surface. Surface defect properties of the catalyst.Electronic and semiconducting properties and the band structure. Co-existence of dilferent types of ions or structures. Adsorption sites and adsorbed species such as oxygen.Preparation method of catalyst , surface area and nature of heat treatment. Molecular structure of the reactants. Many systematic investigations have been performed to correlate catalytic performances with the above mentioned properties. Many of these investigations remain isolated and further research is needed to bridge the gap in the present knowledge of the field.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.