Realization of Optical Logic Gates Using the Thermal Lens Effect

A sensitive method based on the principle of photothermal phenomena to realize optical logic gates is presented. A dual beam thermal lens method using low power cw lasers in a dye-doped polymer can be very effectively used as an alternate technique to perform the logical function such as NAND, AND and OR.

Studies On The Reproduction Of Indian Whiting Sill/160 5'/Ham/1 (Forskal) (Percoidei, Sillaginidae)

From the point of view of rational exploitation and proper management of the fishery resources as well as for the development of intensive aquaculture of fishes through selective breeding, brood stock development, domestication and genetic improvement, a sound knowledge of reproductive biology and physiology of the candidate species is of great importance. In recent times, a wealth of information on maturity, spawning habits, spawning periodicity, spawning season, size at maturity and fecundity of commercially important fishes has been generated. Gametogenesis involves the transformation of Primordial germ cells in the gonads into specialised cells or gametes, namely ova in the female and sperms in male, through a series of complex morphological and cytological events. The formation of male gamete is known as spermatogenesis. In the female, the primary growth phase involving the formation of primary oocyte from oogonia is known as oogenesis, which would be followed by the secondary growth phase, in which considerable increase in the size of the oocyte occurs, due mainly to accumulation of yolk. This process is known as vitellogenesis, which would be followed by final maturation and ovulation of the ova. In the present work, basic aspects of maturation and spawning, salient features of gametogenesis and associated biochemical changes occurring during these processes in an important cultivable fish, Sillago sihama belonging to the family Sillaginidae have been investigated.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.