Numerical Simulation of Two-Part Underwater Towing System

The motion instability is an important issue that occurs during the operation of towed underwater vehicles (TUV), which considerably affects the accuracy of high precision acoustic instrumentations housed inside the same. Out of the various parameters responsible for this, the disturbances from the tow-ship are the most significant one. The present study focus on the motion dynamics of an underwater towing system with ship induced disturbances as the input. The study focus on an innovative system called two-part towing. The methodology involves numerical modeling of the tow system, which consists of modeling of the tow-cables and vehicles formulation. Previous study in this direction used a segmental approach for the modeling of the cable. Even though, the model was successful in predicting the heave response of the tow-body, instabilities were observed in the numerical solution. The present study devises a simple approach called lumped mass spring model (LMSM) for the cable formulation. In this work, the traditional LMSM has been modified in two ways. First, by implementing advanced time integration procedures and secondly, use of a modified beam model which uses only translational degrees of freedoms for solving beam equation. A number of time integration procedures, such as Euler, Houbolt, Newmark and HHT-α were implemented in the traditional LMSM and the strength and weakness of each scheme were numerically estimated. In most of the previous studies, hydrodynamic forces acting on the tow-system such as drag and lift etc. are approximated as analytical expression of velocities. This approach restricts these models to use simple cylindrical shaped towed bodies and may not be applicable modern tow systems which are diversed in shape and complexity. Hence, this particular study, hydrodynamic parameters such as drag and lift of the tow-system are estimated using CFD techniques. To achieve this, a RANS based CFD code has been developed. Further, a new convection interpolation scheme for CFD simulation, called BNCUS, which is blend of cell based and node based formulation, was proposed in the study and numerically tested. To account for the fact that simulation takes considerable time in solving fluid dynamic equations, a dedicated parallel computing setup has been developed. Two types of computational parallelisms are explored in the current study, viz; the model for shared memory processors and distributed memory processors. In the present study, shared memory model was used for structural dynamic analysis of towing system, distributed memory one was devised in solving fluid dynamic equations.

‘Driving Forces of Investment Decisions in Mutual Funds’

Unfortunately, in India it is a fact that most of the investors are not interested in mutual funds. Those who are investing, they are investing only very small amounts. But what is important to be noted here is that when compared to other financial instruments, investments in mutual funds are safer and also yields more returns on the investment portfolio. Moreover as an investment avenue mutual fund is available for those investors who are not willing to take any exposure directly in the security market. It also helps such investors to build their wealth over a period of time. At the retail level, investors are unique and are highly heterogeneous, and the mutual fund schemes' selection will also differ depends on their expectations. Hence, investors’ expectation is a very important factor in this regard that needs to be analysed by all the investment houses. Hence, the factors that drive the investment decisions of individual investors to meet their expectations by investing money in mutual funds need an in-depth analysis. These driving forces include the preference of investors on mutual fund compared to various available avenues of financial investments, risk attitude of investors, influence of characteristics of instruments of mutual funds on investors, the investment specific attitudes of investors, and influence of qualities of fund management on investors. The success of any mutual fund, a popular means of investment, depends on how effectively an Asset Management Company has been able to understand the level of influence of these factors on the decision of investors to invest in mutual funds. For a substantial growth in the mutual fund market, there must be a high level precision in the design and marketing of the products of mutual funds taking into account these driving forces by the Asset Management Companies. Therefore, there is a need to conduct a detailed study on investments in mutual funds in this direction. A review of available literature also revealed that no detailed study on mutual funds has so far been attempted in this direction; hence the present study on Driving Forces of Investment Decisions in Mutual Funds is undertaken.

Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters

In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

Fault Tolerant Error Coding and Detection using Reversible Gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Impact of climate change on hetrotrophic bacterial communities in the water and sediment of kongsfjord in norwegian artic

Considering the extent of warming in the artic region and the resultant changes in the dynamic marine enviornments there is a need to monitor the bacterial diversity in the fjord enviornments especially in terms of cultivable bacteria. The present study reports the diversity of cultivable hetrotrophic bacteria from the water and sediment samples of kongsfjord their growth responses to important enviornmental variables and ability to produce industrially important hydrolytic enzymes.

Characterisation and bioprospecting of cold adapted yeast from water samples of kongsfjord ,Norwegian Artic

A total of 34 yeast isolates were characterized from 4 water samples collected from Kongsfjord at Ny Alseund region of Norwegion Artic during the Indian Artic summer expedition of 2009.They were studied for the effect of tempereture and salt concentration on growth as well as for their ability to produce various hydrolytic enzymes at two different temperatures. Result showed that 5 out of 8 genera were common to all the stations. Cryptococcus was the predominant genera folowed by Trichosporan and Rhodotorula 82% of the yeast isolates were oxidative in nature and except filobasidium all the isolates used nitrate as a nitrogen source for growth. Yeast isolates from all the ststions showed growth at 4 and 20 degree centigarade. These temperatures were chosen as most of the bacterial and yeast isolates showed psychrotrop[hic nature. 94% of the yeast isolates showed growth at 2.0M and lipolytic activity were marginally less than 4.None of the isolates produced amylase enzymes when incubated at 4 and 20. The present study highlights the wide tolerence of the psychrotrophic yeast isolates to temperature and salinity as well as their potential in biotechnology

A REVIEW OF SOIL CONSTITUTIVE MODELS FOR SOIL STRUCTURE INTEREACTION ANALYSIS

Soils are multiphase materials comprised of mineral grains, air voids and water. Soils are not linearly elastic or perfectly plastic for external loading. Various constitutive models are available to describe the various aspects of soil behaviour. But no single soil model can completely describe the behaviour of real soil under all conditions. This paper attempts to compare various soil models and suggest a suitable model for the Soil Structure Interaction analysis especially for Kochi marine clay.

Corrosion Behaviour Of Brass In The Vembanad Estuary, India

Corrosion characteristics of brass panels were investigated in the Vembanad estuarine water (Cochin Harbor), India over a period of one year. The corrosion rate of brass samples during exposure was determined by gravimetric method and fouling on panels was assessed, exposure-wise, in terms of biomass. Corrosion products were identified by X-Ray diffraction. The results of the study were discussed in the light of the seawater characteristics

Dezincification of Epoxy Coated Brass in Cochin Estuary, India

Inhibited α brasses are largely immune to dezincification in most water, but the effect of tin and arsenic addition to α/β brasses is not so reliable or predictable in controlling the problem. There have been many cases of dezincification in duplex brasses in both fresh water and seawater. There is no reliable method of inhibiting the dezincification of two-phase brass despite there are some protection methods such as inhibitors, electro deposition and electro polymerization. Organic coatings are effectively used for the protection of metals due to their capacity to act as a physical barrier between the metal surface and corrosive environment. Hence, epoxy coating on brass was applied and effect of this against dezincification in Cochin estuarine water over a period of one year was studied and reported in this paper