24 resultados para High-speed video


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Tropical cyclones genesis, movement and intensification are highly dependent on its environment both oceanic and atmospheric. This thesis has made a detailed study on the environmental factors related to tropical cyclones of North Indian Ocean basin. This ocean basin has produced only 6% of the global tropical cyclones annually but it has caused maximum loss of human life associated with the strong winds, heavy rain and particularly storm surges that accompany severe cyclones as they strike the heavily populated coastal areas. Atmospheric factors studied in the thesis are the moisture content of the atmosphere, instability of the atmosphere that produces thunderstorms which are the main source of energy for the tropical cyclone, vertical wind shear to which cyclones are highly sensitive and the Sub-Tropical westerly Jetsteram and its Asian high speed center. The oceanic parameters studied are sea surface temperature and heat storage in the top layer of the ocean. A major portion of the thesis has dealt with the three temporal variabilities of tropical cyclone frequency namely intra-seasonal (mainly the influence of Madden Julian Oscillation), inter- annual (the relation with El Nino Southern Oscillation) and decadal variabilities. Regarding decadal variability, a prominent four decade oscillation in the frequency of both tropical cyclones and monsoon depressions unique to the Indian Ocean basin has been brought out. The thesis consists of 9 chapters.

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Light in its physical and philosophical sense has captured the imagination of human mind right from the dawn of civilization. The invention of lasers in the 60’s caused a renaissance in the field of optics. This intense, monochromatic, highly directional radiation created new frontiers in science and technology. The strong oscillating electric field of laser radiation creates a. polarisation response that is nonlinear in character in the medium through which it passes and the medium acts as a new source of optical field with alternate properties. It was in this context, that the field of optoelectronics which encompasses the generation, modulation, transmission etc. of optical radiation has gained tremendous importance. Organic molecules and polymeric systems have emerged as a class of promising materials of optoelectronics because they offer the flexibility, both at the molecular and bulk levels, to optimize the nonlinearity and other suitable properties for device applications. Organic nonlinear optical media, which yield large third-order nonlinearities, have been widely studied to develop optical devices like high speed switches, optical limiters etc. Transparent polymeric materials have found one of their most promising applicationsin lasers, in which they can be used as active elements with suitable laser dyes doped in it. The solid-matrix dye lasers make possible combination of the advantages of solid state lasers with the possibility of tuning the radiation over a broad spectral range. The polymeric matrices impregnated with organic dyes have not yet widely used because of the low resistance of the polymeric matrices to laser damage, their low dye photostability, and low dye stability over longer time of operation and storage. In this thesis we investigate the nonlinear and radiative properties of certain organic materials and doped polymeric matrix and their possible role in device development

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In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

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Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain

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The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

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The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated

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In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

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This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

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The Towed Array electronics is a multi-channel simultaneous real time high speed data acquisition system. Since its assembly is highly manpower intensive, the costs of arrays are prohibitive and therefore any attempt to reduce the manufacturing, assembly, testing and maintenance costs is a welcome proposition. The Network Based Towed Array is an innovative concept and its implementation has remarkably simplified the fabrication, assembly and testing and revolutionised the Towed Array scenario. The focus of this paper is to give a good insight into the Reliability aspects of Network Based Towed Array. A case study of the comparison between the conventional array and the network based towed array is also dealt with