Time-Resolved Photoluminescence in Antimonide and Dilute Nitride Quantum Well Structures

This Master's thesis is devoted to semiconductor samples study using time-resolved photoluminescence. This method allows investigating recombination in semiconductor samples in order to develop quality of optoelectronic device. An additional goal was the method accommodation for low-energy-gap materials. The first chapter gives a brief intercourse into the basis of semiconductor physics. The key features of the investigated structures are noted. The usage area of the results covers saturable semiconductor absorber mirrors, disk lasers and vertical-external-cavity surface-emittinglasers. The experiment set-up is described in the second chapter. It is based on up-conversion procedure using a nonlinear crystal and involving the photoluminescent emission and the gate pulses. The limitation of the method was estimated. The first series of studied samples were grown at various temperatures and they suffered rapid thermal annealing. Further, a latticematched and metamorphically grown samples were compared. Time-resolved photoluminescence method was adapted for wavelengths up to 1.5 µm. The results allowed to specify the optimal substrate temperature for MBE process. It was found that the lattice-matched sample and the metamorphically grown sample had similar characteristics.

Kestomagneettitahtikoneen emulointi digitaalisella signaaliprosessorilla

Sähkökäytön suunnittelussa säätöä voidaan testata useassa tapauksessa reaaliaikasimulaattorilla todellisen laitteiston sijaan. Monet reaaliaikasimulaatioiden perustana käytetyt algoritmit soveltuvat täysinohjatulle invertterisillalle. Eräissä sovelluksissa halutaan kuitenkin käyttää puoliksiohjattua siltaa. Puoliksiohjattulla sillalla mallin kausaalisuus voi kääntyä, mitä perinteiset reaaliaikasimulaattorit eivät pysty simuloimaan Tässä työssä oli tavoitteena kehittää reaaliaikasimulaattori puoliksiohjatulle kestomagneettitahtikonekäytölle. Emulaattoriin mallinnettiin todellisen käytön kestomagneettitahtikone ja invertterisilta. Simulaattori toteutettiin digitaaliselle signaaliprosessorille (DSP) ja mittauksiin liittyvät oheislaitteet mallinnettiin FPGA-piirille. Emulaattoriin liitettiin erillinen säätäjä, jota käytettiin myös todellisen sähkökäytön säätämiseen. Emulaattorilla ja todellisella käytöllä tehtyjä mittauksia verrattiin ja emuloimalla saadut tulokset vastasivat melko hyvin todellisesta käytöstä mitattuja.

IGBT-simulaatiomallien soveltuvuus laitetason hyötysuhdesimulaatioihin

Tehoelektroniikkalaitteiden tehon kasvun myötä niiden hyötysuhteesta on tullut yksi niiden tärkeimmistä ominaisuuksista. Suurilla tehoilla prosentuaalisesti pienetkin tehohäviöt ovat merkittäviä ja aiheuttavat laitteen käyttäjälle ylimääräisiä energiakustannuksia ja tarvetta hukkalämmön poistolle. Näistä syistä asiakkaat vaativat hyvällä hyötysuhteella toimivia laitteita, joten laitevalmistajat pyrkivät tekemään niistä sellaisia. Simulaatiomallit ovat arvokkaita työkaluja laitesuunnittelussa. Hyötysuhdeoptimoinnin kannalta tehohäviöt tulisi pystyä mallintamaan, jotta komponenttivalintojen, ohjaustapojen ja pääpiiritopologioiden vaikutusta hyötysuhteeseen voitaisiin arvioida. Tässä työssä perehdytään eristehilabipolaaritransistorista (IGBT) tehtyihin simulaatiomalleihin ja arvioidaan niiden soveltuvuutta IGBT:ssä syntyvien tehohäviöiden mallintamiseen. Lisäksi verrataan mallia mittaukseen ja pohditaan, millaiset vaatimukset simulaatiomalliin todellisuudessa kohdistuvat.

Switching components for medium voltage drives

Nowadays power drives are the essential part almost of all technological processes. Improvement of efficiency and reduction of losses require development of semiconductor switches. It has a particular meaning for the constantly growing market of renewable sources, especially for wind turbines, which demand more powerful semiconductor devices for control with growth of power. Also at present semiconductor switches are the key component in energy transmission, optimization of generation and network connection. The aim of this thesis is to make a survey of contemporary semiconductor components, showing difference in structures, advantages, disadvantages and most suitable applications. There is topical information about voltage, frequency and current limits of different switches. Study tries to compare dimensions and price of different components. Main manufacturers of semiconductor components are presented with the review of devices produced by them, and a conclusion about their availability was made. IGBT is selected as a main component in this study, because nowadays it is the most attractive component for usage in power drives, especially at the low levels of medium voltage. History of development of IGBT structure, static and dynamic characteristics are considered. Thesis tells about assemblies and connection of components and problems which can appear. One of key questions about semiconductor materials and their future development was considered. For the purpose of comparison strong and weak sides of different switches, calculation of losses of IGBT and its basic competitor – IGCT is presented. This master’s thesis makes an effort to answer the question if there are at present possibilities of accurate selection of switches for electrical drives of different rates of power and looks at future possible ways of development of semiconductor market.

Comparison and Evaluation of Eddy Current Sensors

In the work eddy current sensors are described and evaluated. Theoretical part includes physical basics of the eddy currents, overview of available commercial products and technologies. Industrial sensors operation was assessed based on several working modes. Apart from this, the model was created in Matlab Simulink with Xilinx Blockset and then translated into a Xilinx ISE Design Suite compatible project. The performance of the resulting implementation was compared to the existing implementation in the Xilinx Spartan 3 FPGA board with the custom made sensor. Additionally, an introduction to FPGAs and VHDL is presented.

Active inverter output filtering methods

Frequency converters are widely used in the industry to enable better controllability and efficiency of variable speed AC motor drives. Despite these advantages, certain challenges concerning the inverter and motor interfacing have been present for decades. As insulated gate bipolar transistors entered the market, the inverter output voltage transition rate significantly increased compared with their predecessors. Inverters operate based on pulse width modulation of the output voltage, and the steep voltage edge fed by the inverter produces a motor terminal overvoltage. The overvoltage causes extra stress to the motor insulation, which may lead to a prematuremotor failure. The overvoltage is not generated by the inverter alone, but also by the sum effect of the motor cable length and the impedance mismatch between the cable and the motor. Many solutions have been shown to limit the overvoltage, and the mainstream products focus on passive filters. This doctoral thesis studies an alternative methodology for motor overvoltage reduction. The focus is on minimization of the passive filter dimensions, physical and electrical, or better yet, on operation without any filter. This is achieved by additional inverter control and modulation. The studied methods are implemented on different inverter topologies, varying in nominal voltage and current.For two-level inverters, the studied method is termed active du/dt. It consists of a small output LC filter, which is controlled by an independent modulator. The overvoltage is limited by a reduced voltage transition rate. For multilevel inverters, an overvoltage mitigation method operating without a passive filter, called edge modulation, is implemented. The method uses the capability of the inverter to produce two switching operations in the same direction to cancel the oscillating voltages of opposite phases. For parallel inverters, two methods are studied. They are both intended for two-level inverters, but the first uses individual motor cables from each inverter while the other topology applies output inductors. The overvoltage is reduced by interleaving the switching operations to produce a similar oscillation accumulation as with the edge modulation. The implementation of these methods is discussed in detail, and the necessary modifications to the control system of the inverter are presented. Each method is experimentally verified by operating industrial frequency converters with the modified control. All the methods are found feasible, and they provide sufficient overvoltage protection. The limitations and challenges brought about by the methods are discussed.

Project Master Document adaption in order fulfillment process

This thesis discusses adaption of new project management tool at ABB Oy Motors and Generators business unit, Synchronous Machines profit centre. Thesis studies project modeling in general and buries in the Gate Model used at ABB Synchronous Machines. It is essential to understand Gate Model because this new project management tool, called Project Master Document, is created on the base of the existing project model. Thesis also analyzes goals and structure of Project Master Document in order to ease implementation of this new tool. Project Master Document aims to improved customer order fulfillment by clearing order handover interface. Office process, especially responsibilities and target dates, become also clearer after Master Document implementation. The document is built to be frame for whole order fulfillment process including check points for each gate of project model and updated memos from all project meetings. Furthermore, project progress will be clearly stated by status markings and visualized with colors.

Innovation Project Portfolio Management

Companies today are forced to innovate in order to remain within business. Such innovation projects undertaken by the companies are defined in this study as creative ideas which have been managed through “Stage-Gate” innovation process. This process is used to manage innovation projects as they proceed from being newly created to ready for launching/implementing. This has ensured that the companies manage the innovation project right. However, with so many new creative ideas the companies can come up within limited resources, the companies must rely on Innovation Project Portfolio Management (IPPM) to ensure that they are managing only the right innovation projects. Although, there are many tools and techniques available for use within Project Portfolio Management, there is still no consensus on which are the most effective and no standard framework has been established especially for IPPM. Thus, this study proposes a practical framework for which individual innovative organization can follow as a guideline to manage its innovation project portfolio. The study theoretically first addresses the key differences between project portfolio management of innovation projects and other traditional projects - one of which is the stage nature of innovation projects due to their unclear objectives from the beginning compare to clearly established objectives of traditional projects. Secondly, different tools and techniques which can be used are examined based on the three goals of IPPM: (1) Maximizing the Value of Innovation Project Portfolio: Financial Methods, Decision Trees, Scoring Models and Checklists; (2) Balancing Innovation Project Portfolio: Visual Representations; and (3) Aligning Innovation Project Portfolio with Strategy: Bottom-Up (Scoring Models with Strategic Criteria) and Top-Down (Strategic Buckets). Finally, the two approaches in which IPPM can be integrated with Stage-Gate innovation process are discussed: (1) Gates- Dominated; and (2) Portfolio Reviews-Dominated. Practically, this study investigates IPPM of a case organization, and through analysis of the case study results proposes a practical framework for case organization to improve its current management of innovation project portfolio. This framework is then generalized to propose a final practical framework or guideline for which an innovative organization can follow to manage its innovation project portfolio.

Power cycling lifetime estimation of IGBT power modules based on chip temperature modeling

In this doctoral thesis, methods to estimate the expected power cycling life of power semiconductor modules based on chip temperature modeling are developed. Frequency converters operate under dynamic loads in most electric drives. The varying loads cause thermal expansion and contraction, which stresses the internal boundaries between the material layers in the power module. Eventually, the stress wears out the semiconductor modules. The wear-out cannot be detected by traditional temperature or current measurements inside the frequency converter. Therefore, it is important to develop a method to predict the end of the converter lifetime. The thesis concentrates on power-cycling-related failures of insulated gate bipolar transistors. Two types of power modules are discussed: a direct bonded copper (DBC) sandwich structure with and without a baseplate. Most common failure mechanisms are reviewed, and methods to improve the power cycling lifetime of the power modules are presented. Power cycling curves are determined for a module with a lead-free solder by accelerated power cycling tests. A lifetime model is selected and the parameters are updated based on the power cycling test results. According to the measurements, the factor of improvement in the power cycling lifetime of modern IGBT power modules is greater than 10 during the last decade. Also, it is noticed that a 10 C increase in the chip temperature cycle amplitude decreases the lifetime by 40%. A thermal model for the chip temperature estimation is developed. The model is based on power loss estimation of the chip from the output current of the frequency converter. The model is verified with a purpose-built test equipment, which allows simultaneous measurement and simulation of the chip temperature with an arbitrary load waveform. The measurement system is shown to be convenient for studying the thermal behavior of the chip. It is found that the thermal model has a 5 C accuracy in the temperature estimation. The temperature cycles that the power semiconductor chip has experienced are counted by the rainflow algorithm. The counted cycles are compared with the experimentally verified power cycling curves to estimate the life consumption based on the mission profile of the drive. The methods are validated by the lifetime estimation of a power module in a direct-driven wind turbine. The estimated lifetime of the IGBT power module in a direct-driven wind turbine is 15 000 years, if the turbine is located in south-eastern Finland.

"Fuzzy front end" ja sen menestyksekäs johtaminen teollisuusyrityksessä

Työssä käsitellään innovaatioprosessin ensimmäistä ”fuzzy front end” -vaihetta, jota työssä kutsutaan front end -vaiheeksi. Front end -vaihe on innovaatioprosessin alustava tutkimus ja suunnittelu vaihe ennen teknistä kehittämisvaihetta. Front end -vaihetta on tutkittu innovaatioprosessin osista vähiten, sekä se on useimmille yrityksillä sumea ja vaikeasti käsitettävä. Tutkimusten mukaan front end -vaiheen osaaminen on kuitenkin erittäin merkittävä tekijä yrityksen innovatiivisuudelle. Työssä avataan innovaatioprosessin sisältöä ja tavoitteita, sekä vertaillaan käytössä olevia malleja front end -vaiheen rakenteesta. Työssä selvitetään avaintekijöitä front end -vaiheen menestykseen ja tehokkuuteen. Lisäksi käsitellään johtamisen tekijöitä, jotka edesauttavat onnistumaan front end -vaiheessa.

Ydinprosessikuvaus johtamisen tukena rakennusalan konsernissa

Tämän diplomityön tärkeimpänä tavoitteena on kuvata kohdekonsernin ydinprosessi asiakasrajapinnasta takuutarkastukseen sekä sitä tukevat prosessit riittävällä tarkkuudella. Lisäksi tavoitteena on laatia kuvaamisen pohjalta yksinkertainen työkalu yksittäisten hankkeiden johtamisen sekä sisäisen koulutuksen tarpeisiin. Tavoitteena on työn kautta edistää konsernin strategisten tavoitteiden saavuttamista. Työ jakautuu teoria- ja empiriaosaan. Teoriaosassa luodaan viitekehys työn empiriaosalle. Se pitää sisällään prosessiajattelun ja prosessijohtamisen käsittelyä sekä prosessien kuvaamisen ja niiden suorituskyvyn mittaamisen teoreettista taustaa. Työn empiria- eli käytännön osassa kuvataan konsernin strategian mukainen ydinprosessi ja määritetään siihen porttimallin mukaiset portit sekä niissä tarkastettavat minimivaatimukset. Lisäksi esitellään ydinprosessia tukevia prosesseja ja laaditaan suorituskykymittaristo sekä käsitellään jatkuvaa parantamista konsernissa käytännössä. Käytännön osan lopussa esitellään kuvauksen pohjalta laadittu työkalu sekä sen tuomat mahdollisuudet. Teoriaosa on luonteeltaan kirjallisuustutkimus, joka muodostuu kirjojen ja artikkelien pohjalta. Empiriaosassa on sekä tapaustutkimuksen että konstruktiivisen tutkimuksen piirteitä ja menetelminä siinä on käytetty haastatteluja, palavereita ja havainnointia. Empiriaosassa on hyödynnetty myös konsernin omaa aineistoa. Keskeisimpiä tuloksia ovat ydinprosessin kuvaus sekä sen pohjalta laadittu konsernin tarpeisiin vastaava konkreettinen työkalu. Lisäksi tuloksena voidaan pitää havaittua prosessiajattelun edistymistä konsernissa. Kohdekonsernin ydinprosessi koostuu kuudesta vaiheesta: 1) asiakastarpeiden selvitys/myynti, 2) tarjous- ja sopimusvaihe, 3) suunnittelu, 4) työmaavaihe, 5) ennakkotarkastus- ja luovutusvaihe ja 6) loppuselvitys- ja takuuvaihe. Ydinprosessin vaiheet muodostuvat määriteltyjen porttien kautta ja ne muodostavat konsernin prosessikartan rungon.

Research and development of III-V semiconductor surfaces for improved device interfaces

This thesis is devoted to understanding and improving technologically important III-V compound semiconductor (e.g. GaAs, InAs, and InSb) surfaces and interfaces for devices. The surfaces and interfaces of crystalline III-V materials have a crucial role in the operation of field-effect-transistors (FET) and highefficiency solar-cells, for instance. However, the surfaces are also the most defective part of the semiconductor material and it is essential to decrease the amount of harmful surface or interface defects for the next-generation III-V semiconductor device applications. Any improvement in the crystal ordering at the semiconductor surface reduces the amount of defects and increases the material homogeneity. This is becoming more and more important when the semiconductor device structures decrease to atomic-scale dimensions. Toward that target, the effects of different adsorbates (i.e., Sn, In, and O) on the III-V surface structures and properties have been investigated in this work. Furthermore, novel thin-films have been synthesized, which show beneficial properties regarding the passivation of the reactive III-V surfaces. The work comprises ultra-high-vacuum (UHV) environment for the controlled fabrication of atomically ordered III-V(100) surfaces. The surface sensitive experimental methods [low energy electron diffraction (LEED), scanning tunneling microscopy/spectroscopy (STM/STS), and synchrotron radiation photoelectron spectroscopy (SRPES)] and computational density-functionaltheory (DFT) calculations are utilized for elucidating the atomic and electronic properties of the crucial III-V surfaces. The basic research results are also transferred to actual device tests by fabricating metal-oxide-semiconductor capacitors and utilizing the interface sensitive measurement techniques [capacitance voltage (CV) profiling, and photoluminescence (PL) spectroscopy] for the characterization. This part of the thesis includes the instrumentation of home-made UHV-compatible atomic-layer-deposition (ALD) reactor for growing good quality insulator layers. The results of this thesis elucidate the atomic structures of technologically promising Sn- and In-stabilized III-V compound semiconductor surfaces. It is shown that the Sn adsorbate induces an atomic structure with (1×2)/(1×4) surface symmetry which is characterized by Sn-group III dimers. Furthermore, the stability of peculiar ζa structure is demonstrated for the GaAs(100)-In surface. The beneficial effects of these surface structures regarding the crucial III-V oxide interface are demonstrated. Namely, it is found that it is possible to passivate the III-V surface by a careful atomic-scale engineering of the III-V surface prior to the gate-dielectric deposition. The thin (1×2)/(1×4)-Sn layer is found to catalyze the removal of harmful amorphous III-V oxides. Also, novel crystalline III-V-oxide structures are synthesized and it is shown that these structures improve the device characteristics. The finding of crystalline oxide structures is exploited by solving the atomic structure of InSb(100)(1×2) and elucidating the electronic structure of oxidized InSb(100) for the first time.

Universal Quantum Cloning

After introducing the no-cloning theorem and the most common forms of approximate quantum cloning, universal quantum cloning is considered in detail. The connections it has with universal NOT-gate, quantum cryptography and state estimation are presented and briefly discussed. The state estimation connection is used to show that the amount of extractable classical information and total Bloch vector length are conserved in universal quantum cloning. The 1  2 qubit cloner is also shown to obey a complementarity relation between local and nonlocal information. These are interpreted to be a consequence of the conservation of total information in cloning. Finally, the performance of the 1  M cloning network discovered by Bužek, Hillery and Knight is studied in the presence of decoherence using the Barenco et al. approach where random phase fluctuations are attached to 2-qubit gates. The expression for average fidelity is calculated for three cases and it is found to depend on the optimal fidelity and the average of the phase fluctuations in a specific way. It is conjectured to be the form of the average fidelity in the general case. While the cloning network is found to be rather robust, it is nevertheless argued that the scalability of the quantum network implementation is poor by studying the effect of decoherence during the preparation of the initial state of the cloning machine in the 1 ! 2 case and observing that the loss in average fidelity can be large. This affirms the result by Maruyama and Knight, who reached the same conclusion in a slightly different manner.

Some reformulations for the quadratic assignment problem

Kombinatorisk optimering handlar om att hitta en bra eller rent av den bästa möjliga lösningen från ett känt antal lösningar eller kombinationer. Ofta är antalet lösningar så enormt att en genomgång av alla olika lösningar inte är möjlig. En av huvudorsakerna till att det forskas inom kombinatorisk optimering är att liknande frågeställningar eller problem uppkommer inom så många olika områden. Påståendet stämmer speciellt bra för kvadratiska tilldelningsproblem(eng. Quadratic Assignment Problem). Sådana problem uppstår då man försöker beskriva en stor mängd tillämpade frågeställningar. Vilken gate skall väljas för flygen på större flygplatser för att minimera den totala väg människorna behöver gå och bagaget förflyttas? Var skall olika avdelningar på en fabrik placeras för att minimera materialförflyttningar mellan avdelningarna? Hur ser ett optimalt tangentbord ut för olika språk? Var skall komponenterna placeras på ett kretskort? De här är alla frågor som kan besvaras genom att lösa kvadratiska tilldelningsproblem. Kvadratiska tilldelningsproblem är dock mycket svåra att lösa. Det beror på att problemet i den standardform det matematiskt formuleras i huvudsak består av produkter av binära variabler. I denna avhandling har problemet omformulerats till en linjär diskret form som innehåller färre variabler. Med omformuleringen har bland annat flera tidigare olösta kvadratiska tilldelningsproblem kunnat lösas till globalt optimum, den bästa möjliga lösningen, för första gången någonsin.

Tuotelanseerausprosessin kehittäminen

Työn lähtökohtana on vuonna 2009 case-yksikölle luotu stage-gate-malli, jonka ymmärtäminen ja käyttö ei ole ollut toivotulla tasolla. Asenteet ja perehdytys tämän mallin käyttöön ovat aiheuttaneet sen, että osa yksikön henkilöstöstä ei tunnista mallin käyttöä omassa työssään, vaikka sitä käytetään jokaisessa tuotekehitysprojektissa. Työn tavoitteena on kuvata case-yksikön stage-gate-mallin etenemistä selkeämmin, jotta se saataisiin tehokkaammin käyttöön koko henkilöstölle, sekä tutkia ovatko eri toimintojen roolitukset mallin mukaan optimaaliset. Tavoitteena on myös tutkia kuinka tiedon tulisi kulkea toimintojen välillä, jotta se olisi mahdollisimman tehokasta. Työtä varten on kerätty kirjallisuusmateriaalia teorian pohjustamiseksi ja haastateltu 14 yksikön toimihenkilöä nykyisten ongelmakohtien kartoittamiseksi. Lisäksi työhön liittyen tehtiin benchmark-haastattelu mahdollisimman lähellä case-yksikön liiketoimintaa olevasta saman yrityksen yksiköstä. Yksikölle luodun stage-gate-mallin tuntemus oli haastattelujen perusteella suhteellisen heikolla tasolla. Vain noin puolet tunnisti sen jokapäiväisessä työskentelyssään. Ongelmakohtia mallin käyttämiseen liittyen ilmeni paljon ja niistä iso osa kohdistui myyntiin, markkinointiin sekä projektipäällikön toimintaan. Havaittujen ongelmien perusteella yksikön roolituksista tehtiin selventävä kaavio, jotta jokaisen on helpompi hahmottaa prosessia. Lisäksi henkilöstön osallistamiseen ja tiedonjakamiseen annettiin kehitysehdotuksia. Näin ollen koko henkilöstö saadaan ymmärtämään mallin vaiheet ja tärkeimpänä, ymmärtämään oman roolinsa kussakin stage-gate-mallin vaiheessa.