Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Métodos de extracción de parámetros de un circuito equivalente de pequeña señal para transistores LDMOS de potencia para aplicaciones de RF

En la actualidad, la gran cantidad de aplicaciones que surgen dentro del ámbito de la radiofrecuencia hacen que el desarrollo de dispositivos dentro de este campo sea constante. Estos dispositivos cada vez requieren mayor potencia para frecuencias de trabajo elevadas, lo que sugiere abrir vías de investigación sobre dispositivos de potencia que ofrezcan los resultados deseados para altas frecuencias de operación (GHz). Dentro de este ámbito, el objetivo principal de este proyecto es el de realizar un estudio sobre este tipo de dispositivos, siendo el transistor LDMOS el candidato elegido para tal efecto, debido a su buen comportamiento en frecuencia para tensiones elevadas de funcionamiento.

Direct modulation of electroluminescence from silicon nanocrystals beyond radiative recombination rates

We propose a light emitting transistor based on silicon nanocrystals provided with 200 Mbits/ s built-in modulation. Suppression of electroluminescence from silicon nanocrystals embedded into the gate oxide of a field effect transistor is achieved by fast Auger quenching. In this process, a modulating drain signal causes heating of carriers in the channel and facilitates the charge injection into the nanocrystals. This excess of charge enables fast nonradiative processes that are used to obtain 100% modulation depths at modulating voltages of 1 V.

A time-domain method for the analysis of thermal impedance response preserving the convolution form

The study of the thermal behavior of complex packages as multichip modules (MCM¿s) is usually carried out by measuring the so-called thermal impedance response, that is: the transient temperature after a power step. From the analysis of this signal, the thermal frequency response can be estimated, and consequently, compact thermal models may be extracted. We present a method to obtain an estimate of the time constant distribution underlying the observed transient. The method is based on an iterative deconvolution that produces an approximation to the time constant spectrum while preserving a convenient convolution form. This method is applied to the obtained thermal response of a microstructure as analyzed by finite element method as well as to the measured thermal response of a transistor array integrated circuit (IC) in a SMD package.

Design and construction of precision heat fluxmeters

InAlAs/InGaAs/InP based high electron mobility transistor devices have been structurally and electrically characterized, using transmission electron microscopy and Raman spectroscopy and measuring Hall mobilities. The InGaAs lattice matched channels, with an In molar fraction of 53%, grown at temperatures lower than 530¿°C exhibit alloy decomposition driving an anisotropic InGaAs surface roughness oriented along [1math0]. Conversely, lattice mismatched channels with an In molar fraction of 75% do not present this lateral decomposition but a strain induced roughness, with higher strength as the channel growth temperature increases beyond 490¿°C. In both cases the presence of the roughness implies low and anisotropic Hall mobilities of the two dimensional electron gas.

Modeling and manufacturability assessment of bistable quantum-dot cells

We have investigated the behavior of bistable cells made up of four quantum dots and occupied by two electrons, in the presence of realistic confinement potentials produced by depletion gates on top of a GaAs/AlGaAs heterostructure. Such a cell represents the basic building block for logic architectures based on the concept of quantum cellular automata (QCA) and of ground state computation, which have been proposed as an alternative to traditional transistor-based logic circuits. We have focused on the robustness of the operation of such cells with respect to asymmetries derived from fabrication tolerances. We have developed a two-dimensional model for the calculation of the electron density in a driven cell in response to the polarization state of a driver cell. Our method is based on the one-shot configuration-interaction technique, adapted from molecular chemistry. From the results of our simulations, we conclude that an implementation of QCA logic based on simple ¿hole arrays¿ is not feasible, because of the extreme sensitivity to fabrication tolerances. As an alternative, we propose cells defined by multiple gates, where geometrical asymmetries can be compensated for by adjusting the bias voltages. Even though not immediately applicable to the implementation of logic gates and not suitable for large scale integration, the proposed cell layout should allow an experimental demonstration of a chain of QCA cells.

Electronic properties of a quantum wire with arbitrary bending angle

The electron transmission and bound state properties of a quantum wire with a sharp bend at arbitrary angle are studied, extending results on the right angle sharp bend (the L¿shaped wire). These new results are compared to those of a similar structure, the circular bend wire. The possibility of using a bent wire to perform transistor action is also discussed.

Theory of surface noise under Coulomb correlations between carriers and surface states

We present a theory of the surface noise in a nonhomogeneous conductive channel adjacent to an insulating layer. The theory is based on the Langevin approach which accounts for the microscopic sources of fluctuations originated from trapping¿detrapping processes at the interface and intrachannel electron scattering. The general formulas for the fluctuations of the electron concentration, electric field as well as the current-noise spectral density have been derived. We show that due to the self-consistent electrostatic interaction, the current noise originating from different regions of the conductive channel appears to be spatially correlated on the length scale correspondent to the Debye screening length in the channel. The expression for the Hooge parameter for 1/f noise, modified by the presence of Coulomb interactions, has been derived