Low noise pixel detectors based on gated geiger mode avalanche photodiodes

The gated operation is proposed as an effective method to reduce the noise in pixel detectors based on Geiger mode avalanche photodiodes. A prototype with the sensor and the front-end electronics monolithically integrated has been fabricated with a conventional HV-CMOS process. Experimental results demonstrate the increase of the dynamic range of the sensor by applying this technique.

Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to erroneous results and limit the range of detectable signals. They also increase the amount of data that has to be stored. In this work, we present a pixel based on a Geiger-mode avalanche photodiode operated in the gated mode to reduce the probability to detect noise counts interfering with photon arrival events. The readout circuit is based on a two grounds scheme to enable low reverse bias overvoltages and consequently lessen the dark count rate. Experimental characterization of the fabricated pixel with the HV-AMS 0.35µm standard technology is also presented in this article.

Continuous phase shift of sinusoidal signals using injection locked oscillators

This work presents an alternative to generate continuous phase shift of sinusoidal signals based on the use of super harmonic injection locked oscillators (ILO). The proposed circuit is a second harmonic ILO with varactor diodes as tuning elements. In the locking state, by changing the varactor bias, a phase shift instead of a frequency shift is observed at the oscillator output. By combining two of these circuits, relative phases up to 90 could be achieved. Two prototypes of the circuit have been implemented and tested, a hybrid version working in the range of 200-300 MHz and a multichip module (MCM) version covering the 900¿1000 MHz band.

A current-mode interface circuit for a piezoresistive pressure sensor

An interfacing circuit for piezoresistive pressure sensors based on CMOS current conveyors is presented. The main advantages of the proposed interfacing circuit include the use of a single piezoresistor, the capability of offset compensation, and a versatile current-mode configuration, with current output and current or voltage input. Experimental tests confirm linear relation of output voltage versus piezoresistance variation.

Electroluminiscence and optical amplification in silicon nanostructures: towards the integration of electronics and photonics

This line of research of my group intends to establish a Silicon technological platform in the field of photonics allowing the development of a wide set of applications. Particularly, what is still lacking in Silicon Photonics is an efficient and integrable light source such an LED or laser. Nanocrystals in silicon oxide or nitride matrices have been recently demonstrated as competitive materials for both active components (electrically and optically driven light emitters and optical amplifiers) and passive ones (waveguides and modulators). The final goal is the achievement of a complete integration of electronic and optical functions in the same CMOS chip. The first part of this paper will introduce the structural and optical properties of LEDs fabricated from silicon nanostructures. The second will treat the interaction of such nanocrystals with rare-earth elements (Er), which lead to an efficient hybrid system emitting in the third window of optical fibers. I will present the fabrication and assessment of optical waveguide amplifiers at 1.54 ¿m for which we have been able to demonstrate recently optical gain in waveguides made from sputtered silicon suboxide materials.

Power supply noise and logic error probability

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays anda noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in thispaper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanismsand shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Error probability in synchronous digital circuits due to power supply noise

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits.The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recoveringtechniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

Voltage fluctuations in IC power supply distribution

The supply voltage decrease and powerconsumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at thesame voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze the effect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated.