Multi-μ: an Ada 95 based architecture for fault tolerance support of real-time systems

This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Efeitos Imediatos da Mobilização com Movimento na Rotação Medial da Gleno-umeral em Jogadores de Andebol

Introdução: No andebol, o ombro é elevado numa amplitude superior a 90º e move-se com elevada velocidade de execução o que pode originar deslocação anterior da cabeça do úmero e diminuição da rotação medial. A técnica MWM pode ser uma mais valia na correção da falha posicional e recuperação da amplitude de movimento de rotação medial da articulação gleno-umeral. Objetivo: Este estudo teve como objetivo verificar os efeitos imediatos da técnica de MWM na amplitude de movimento de rotação medial da articulação gleno-umeral em jogadores de andebol. Métodos: O presente estudo, duplamente cego, é do tipo experimental. Foram incluídos no estudo 30 indivíduos do sexo masculino, jogadores de andebol, distribuídos, aleatoriamente, em dois grupos de 15, experimental e controlo. Em ambos os grupos foi avaliada a amplitude de movimento da rotação medial da gleno-umeral, em dois momentos, pré e pós intervenção. O grupo experimental foi submetido à técnica de MWM no movimento de rotação medial da gleno-umeral no membro dominante. Ao grupo de controlo, foi solicitada a realização do movimento ativo de rotação medial no membro dominante, o fisioterapeuta manteve os mesmos contactos manuais mas não aplicou pressão na cabeça do úmero. Para a comparação entre os grupos experimental e controlo recorreu-se ao teste de Mann-Whitney e para analisar diferenças entre os dois momentos, para cada grupo, foi utilizado o teste de Wilcoxon. Resultados: Foram encontradas diferenças significativas no grupo experimental e controlo, contudo essa diferença foi superior no grupo experimental. Após a intervenção, o grupo experimental apresentou amplitudes de rotação medial da gleno-umeral significativamente mais elevadas às do grupo de controlo (U=0,50; p <0,001). Conclusão: A técnica de MWM para rotação medial produziu um aumento significativo na amplitude desse movimento.

Exoneração do Passivo Restante

A atual crise económica determinou um aumento significativo de casos de insolvência de pessoas singulares, uma vez que as famílias, para verem satisfeitas as suas necessidades, recorrem, por vezes em demasia, a instituições de crédito, o que leva ao seu sobreendividamento. Deste modo, o processo de insolvência pode ser o último recurso para as pessoas singulares resolverem a sua situação de incumprimento. Entre as medidas aplicáveis às pessoas singulares destaca-se a exoneração do passivo restante, prevista nos artigos 235.º a 248.º do CIRE. Esta solução dá aos devedores a possibilidade de se libertarem de algumas das suas dívidas com vista à sua reabilitação económica. É nisto que se traduz o princípio do fresh start. Este trabalho tem por objeto a insolvência de pessoas singulares, em especial a exoneração do passivo restante e o fundamento de indeferimento liminar do pedido de exoneração baseado na culpa do devedor na criação ou agravamento da sua situação de insolvência, constante do artigo 238º nº 1 al. e) do CIRE.