Reconfigurable antenna for mobile devices

O trabalho descrito nesta dissertação de mestrado foca-se em geral na investigação de antenas impressas. São apresentados conceitos básicos, em conjunto com alguns exemplos desenvolvidos. No entanto, o principal foco prende-se com técnicas de miniaturização e reconfigurabilidade de antenas. A miniaturização de antenas é um tema de investigação de longa data, no entanto, novas técnicas e soluções são apresentadas regularmente. Nesta tese, é aplicada uma técnica recente, baseada na introdução de indutores encapsulados no elemento ressonante de uma antena, que permite miniaturizar um monopólio impresso com uma frequência de ressonância de 2.5 GHz. Outro assunto abordado neste trabalho é a reconfigurabilidade de antenas. Algumas das técnicas mais comuns na investigação actual são apresentadas e debatidas. Uma solução com recurso a díodos PIN é usada para estudar esta capacidade. Os conceitos e características deste tipo de componentes são apresentadas sendo feito o desenho e fabrico de um possível monopólio impresso reconfigurável para operação em dupla banda. Por fim, são combinadas as técnicas de miniaturização com inductor encapsulado e reconfigurabilidade através de díodos PIN, por forma a projectar uma antena reconfigurável muito pequena, para operação em duas bandas distintas. Os resultados são discutidos e com base nestes, algumas possíveis otimizações são propostas. The work reported in this dissertation is focused in the printed antenna research. Basic concepts of printed antennas are presented, along with a few examples that were developed. The main focus however, is around miniaturization and reconfigurability of antennas. Antenna miniaturization is a long time research subject, however, new techniques and solutions are presented everyday. In this thesis, a recent technique based on the introduction of chip inductors in the resonating element of a printed antenna is used in order to miniaturize a monopole with a resonating frequency at 2.5 GHz. Another issue approached in this work is antenna reconfigurability. Some common techniques used in antenna reconfiguration are presented and debated. A solution with PIN diodes is used to study this capability. The concepts and characteristics of this type of components are presented and an example of a reconfigurable printed monopole for dual-band operation is designed and fabricated. At last, miniaturization with chip inductor and reconfigurability through PIN diodes are used together to create a very small antenna for dual-band operation. The simulated and measured results are discussed and upon these, some possible optimizations are proposed.

Multilayer Architectures Based on a-SiC:H Material: Tunable Wavelength Filters in Optical Processing Devices

The characteristics of tunable wavelength filters based on a-SiC:H multilayered stacked pin cells are studied both theoretically and experimentally. The optical transducers were produced by PECVD and tested for a proper fine tuning of the cyan and yellow fluorescent proteins emission. The active device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructures sandwiched between two transparent contacts. Experimental data on spectral response analysis, current-voltage characteristics and color and transmission rate discrimination are reported. Cyan and yellow fluorescent input channels were transmitted together, each one with a specific transmission rate and different intensities. The multiplexed optical signal was analyzed by reading out, under positive and negative applied voltages, the generated photocurrents. Results show that the optimized optical transducer has the capability of combining the transient fluorescent signals onto a single output signal without losing any specificity (color and intensity). It acts as a voltage controlled optical filter: when the applied voltages are chosen appropriately the transducer can select separately the cyan and yellow channel emissions (wavelength and frequency) and also to quantify their relative intensities. A theoretical analysis supported by a numerical simulation is presented.

Optoelectronic Logic Functions Based on Reconfigurable SiC Multilayer Devices

WDM multilayered SiC/Si devices based on a-Si:H and a-SiC:H filter design are approached from a reconfigurable point of view. Results show that the devices, under appropriated optical bias, act as reconfigurable active filters that allow optical switching and optoelectronic logic functions development. Under front violet irradiation the magnitude of the red and green channels are amplified and the blue and violet reduced. Violet back irradiation cuts the red channel, slightly influences the magnitude of the green and blue ones and strongly amplifies de violet channel. This nonlinearity provides the possibility for selective removal of useless wavelengths. Particular attention is given to the amplification coefficient weights, which allow taking into account the wavelength background effects when a band needs to be filtered from a wider range of mixed signals, or when optical active filter gates are used to select and filter input signals to specific output ports in WDM communication systems. A truth table of an encoder that performs 8-to-1 multiplexer (MUX) function is presented.

Reconfigurable SiC Embedded Photonic Structures with Self Optical Bias Control

Multilayered heterostructures based on embedded a-Si:H and a-SiC:H p-i-n filters are analyzed from differential voltage design perspective using short- and long-pass filters. The transfer functions characteristics are presented. A numerical simulation is presented to explain the filtering properties of the photonic devices. Several monochromatic pulsed lights, separately (input channels) or in a polychromatic mixture (multiplexed signal) at different bit rates, illuminated the device. Steady-state optical bias is superimposed from the front and the back side. Results show that depending on the wavelength of the external background and impinging side, the device acts either as a short- or a long-pass band filter or as a band-stop filter. Particular attention is given to the amplification coefficient weights, which allow to take into account the wavelength background effects when a band or frequency needs to be filtered or the gate switch, in which optical active filter gates are used to select and filter input signals to specific output ports in wavelength division multiplexing (WDM) communication systems. This nonlinearity provides the possibility for selective removal or addition of wavelengths. A truth table of an encoder that performs 8-to-1 MUX function exemplifies the optoelectronic conversion.

Optical processing devices based on a-SiCH multilayer architectures

Red, green and blue optical signals were directed to an a-SiC:H multilayered device, each one with a specific transmission rate. The combined optical signal was analyzed by reading out, under different applied voltages, the generated photocurrent. Results show that when a chromatic time dependent wavelength combination with different transmission rates irradiates the multilayered structure, the device operates as a tunable wavelength filter and can be used in wavelength division multiplexing systems for short range communications. An application to fluorescent proteins detection is presented. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Intermodulation in active reconfigurable antennas

Due to the application of active components into antennas these became a source of distortion on wireless communication systems. In this paper we explore the nonlinear effects occurring in a frequency reconfigurable antenna operating with a PIN Diode. We describe the measurement setup used to check the antenna intermodulation products and the measured compression and third order intermodulation limitations of a frequency reconfigurable antenna, operating at the UMTS and WLAN frequencies.

Performance comparison of a VDFLL versus VDLL and scalar GNSS receiver architectures in Harsh scenarios

We analyze the advantages and drawbacks of a vector delay/frequency-locked loop (VDFLL) architecture regarding the conventional scalar and the vector delay-locked loop (VDLL) architectures for GNSS receivers in harsh scenarios that include ionospheric scintillation, multipath, and high dynamics motion. The VDFLL is constituted by a bank of code and frequency discriminators feeding a central extended Kaiman filter (EKF) that estimates the receiver's position, velocity, and clock bias. Both code and frequency loops are closed vectorially through the EKF. The VDLL closes the code loop vectorially and the phase loops through individual PLLs while the scalar receiver closes both loops by means of individual independent PLLs and DLLs.

Compact, frequency reconfigurable, printed monopole antenna

This paper proposes a possible implementation of a compact printed monopole antenna, useful to operate in UMTS and WLAN bands. In order to accomplish that, a miniaturization technique based on the application of chip inductors is used in conjunction with frequency reconfiguration capability. The chip inductors change the impedance response of the monopole, allowing to reduce the resonant frequency. In order to be able to operate the antenna in these two different frequencies, an antenna reconfiguration technique based on PIN diodes is applied. This procedure allows the change of the active form of the antenna leading to a shift in the resonant frequency. The prototype measurements show good agreement with the simulation results.

Reconfigurable antenna for mobile terminal

Trabalho Final de Mestrado para obtenção do grau de Mestrado em Engenharia Electrónica e Telecomunicações

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Biofunctional composite coating architectures based on polycaprolactone and nanohydroxyapatite for controlled corrosion activity and enhanced biocompatibility of magnesium AZ31 alloy

In this work a biofunctional composite coating architecture for controlled corrosion activity and enhanced cellular adhesion of AZ31 Mg alloys is proposed. The composite coating consists of a polycaprolactone (PCL) matrix modified with nanohydroxyapatite (HA) applied over a nanometric layer of polyetherimide (PEI). The protective properties of the coating were studied by electrochemical impedance spectroscopy (EIS), a non-disturbing technique, and the coating morphology was investigated by field emission scanning electron microscopy (FE-SEM). The results show that the composite coating protects the AZ31 substrate. The barrier properties of the coating can be optimized by changing the PCL concentration. The presence of nanohydroxyapatite particles influences the coating morphology and decreases the corrosion resistance. The biocompatibility was assessed by studying the response of osteoblastic cells on coated samples through resazurin assay, confocal laser scanning microscopy (CLSM) and scanning electron microscopy (SEM). The results show that the polycaprolactone to hydroxyapatite ratio affects the cell behavior and that the presence of hydroxyapatite induces high osteoblastic differentiation. (C) 2014 Elsevier B.V. All rights reserved.

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

Stacked pin Devices for Imaging Applications

In this paper we present results on the optimization of device architectures for colour and imaging applications, using a device with a TCO/pinpi'n/TCO configuration. The effect of the applied voltage on the color selectivity is discussed. Results show that the spectral response curves demonstrate rather good separation between the red, green and blue basic colors. Combining the information obtained under positive and negative applied bias a colour image is acquired without colour filters or pixel architecture. A low level image processing algorithm is used for the colour image reconstruction.

Digital radiology and Picture Archiving and Communication System (PACS)

Plain radiography still accounts for the vast majority of imaging studies that are performed at multiple clinical instances. Digital detectors are now prominent in many imaging facilities and they are the main driving force towards filmless environments. There has been a working paradigm shift due to the functional separation of acquisition, visualization, and storage with deep impact in the imaging workflows. Moreover with direct digital detectors images are made available almost immediately. Digital radiology is now completely integrated in Picture Archiving and Communication System (PACS) environments governed by the Digital Imaging and Communications in Medicine (DICOM) standard. In this chapter a brief overview of PACS architectures and components is presented together with a necessarily brief account of the DICOM standard. Special focus is given to the DICOM digital radiology objects and how specific attributes may now be used to improve and increase the metadata repository associated with image data. Regular scrutiny of the metadata repository may serve as a valuable tool for improved, cost-effective, and multidimensional quality control procedures.