A DC Voltage-Multiplier Circuit Working as a High-Voltage Pulse Generator

The intensive use of semiconductor devices enabled the development of a repetitive high-voltage pulse-generator topology from the dc voltage-multiplier (VM) concept. The proposed circuit is based on an odd VM-type circuit, where a number of dc capacitors share a common connection with different voltage ratings in each one, and the output voltage comes from a single capacitor. Standard VM rectifier and coupling diodes are used for charging the energy-storing capacitors, from an ac power supply, and two additional on/off semiconductors in each stage, to switch from the typical charging VM mode to a pulse mode with the dc energy-storing capacitors connected in series with the load. Results from a 2-kV experimental prototype with three stages, delivering a 10-mu s pulse with a 5-kHz repetition rate into a resistive load, are discussed. Additionally, the proposed circuit is compared against the solid-state Marx generator topology for the same peak input and output voltages.

Solid-State Bipolar Marx Generator with Voltage Droop Compensation

This paper addresses the voltage droop compensation associated with long pulses generated by solid-stated based high-voltage Marx topologies. In particular a novel design scheme for voltage droop compensation in solid-state based bipolar Marx generators, using low-cost circuitry design and control, is described. The compensation consists of adding one auxiliary PWM stage to the existing Marx stages, without changing the modularity and topology of the circuit, which controls the output voltage and a LC filter that smoothes the voltage droop in both the positive and negative output pulses. Simulation results are presented for 5 stages Marx circuit using 1 kV per stage, with 1 kHz repetition rate and 10% duty cycle.

Solid-State Bipolar Marx Converter with Output Transformer and Energy Recovery

The purpose of this paper is to present and discuss a general HV topology of the solid-state Marx modulator, for unipolar or bipolar generation connected with a step-up transformer to increase the output voltage applied to a resistive load. Due to the use of an output transformer, discussion about the reset of the transformer is made to guarantee zero average voltage applied to the primary. It is also discussed the transformer magnetizing energy recovering back to the energy storage capacitors. Simulation results for a circuit that generates 100 kV pulses using 1000 V semiconductors are presented and discussed regarding the voltage and current stress on the semiconductors and result obtained.

Projecto e implementação de um sistema de alimentação para um transformador de alta tensão

Neste trabalho pretende-se estudar, dimensionar e implementar experimentalmente de um sistema de alimentação para transformadores de alta tensão a alta frequência. Este sistema será constituído por dois elementos principais, um rectificador monofásico em ponte totalmente controlado e por um inversor de tensão. Inicialmente realizou-se um estudo sobre as diferentes topologias possíveis para o rectificador considerando diferentes tipos de carga. Realizou-se, também, um estudo sobre o circuito de geração dos impulsos de disparo dos tiristores, executado com base num circuito integrado TCA 785, dimensionou-se os elementos constituintes do circuito de disparo, e de um sistema de controlo da tensão de saída do rectificador. Posteriormente estudou-se o funcionamento do inversor de tensão, definindo-se os modos de operação e dimensionou-se um circuito ressonante tendo em conta os parâmetros construtivos do transformador que se pretende utilizar. Finalmente procedeu-se à implementação prática dos sistemas previamente dimensionados e simulados e à apresentação dos respectivos resultados.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Projecto de um regulador linear de tensão: LDO

Os reguladores de tensão LDO são utilizados intensivamente na actual indústria de electrónica, são uma parte essencial de um bloco de gestão de potência para um SoC. O aumento de produtos portáteis alimentados por baterias levou ao crescimento de soluções totalmente integradas, o que degrada o rendimento dos blocos analógicos que o constituem face às perturbações introduzidas na alimentação. Desta forma, surge a necessidade de procurar soluções cada vez mais optimizadas, impondo assim novas soluções, e/ou melhoramentos dos circuitos de gestão de potência, tendo como objectivo final o aumento do desempenho e da autonomia dos dispositivos electrónicos. Normalmente este tipo de reguladores tem a corrente de saída limitada, devido a problemas de estabilidade associados. Numa tentativa de evitar a instabilidade para as correntes de carga definidas e aumentar o PSRR do mesmo, é apresentado um método de implementação que tem como objectivo melhorar estas características, em que se pretende aumentar o rendimento e melhorar a resposta à variação da carga. No entanto, a técnica apresentada utiliza polarização adaptativa do estágio de potência, o que implica um aumento da corrente de consumo. O regulador LDO foi implementado na tecnologia CMOS UMC 0.18μm e ocupa uma área inferior a 0,2mm2. Os resultados da simulação mostram que o mesmo suporta uma transição de corrente 10μA para 100mA, com uma queda de tensão entre a tensão de alimentação e a tensão de saída inferior a 200mV. A estabilidade é assegurada para todas as correntes de carga. O tempo de estabelecimento é inferior a 6μs e as variações da tensão de saída relativamente a seu valor nominal são inferiores a 5mV. A corrente de consumo varia entre os 140μA até 200μA, o que permite atingir as especificações proposta para um PSRR de 40dB@10kHz.

Start-up circuit for low-power indoor light energy harvesting applications

A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm(2). Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

Fonte de carga de condensadores de alta tensão com compensação de fator potência

Trabalho Final de Mestrado para a obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Fifth harmonic and sag impact on PMSG wind turbines with a balancing new strategy for capacitor voltages

This paper deals with the computing simulation of the impact on permanent magnet synchronous generator wind turbines due to fifth harmonic content and grid voltage decrease. Power converter topologies considered in the simulations are the two-level and the three-level ones. The three-level converters are limited by unbalance voltages in the DC-link capacitors. In order to lessen this limitation, a new control strategy for the selection of the output voltage vectors is proposed. Controller strategies considered in the simulation are respectively based on proportional integral and fractional-order controllers. Finally, a comparison between the results of the simulations with the two controller strategies is presented in order to show the main advantage of the proposed strategy. (C) 2014 Elsevier Ltd. All rights reserved.

Predictive Optimal Matrix Converter Control for a Dynamic Voltage Restorer with Flywheel Energy Storage

This paper presents a predictive optimal matrix converter controller for a flywheel energy storage system used as Dynamic Voltage Restorer (DVR). The flywheel energy storage device is based on a steel seamless tube mounted as a vertical axis flywheel to store kinetic energy. The motor/generator is a Permanent Magnet Synchronous Machine driven by the AC-AC Matrix Converter. The matrix control method uses a discrete-time model of the converter system to predict the expected values of the input and output currents for all the 27 possible vectors generated by the matrix converter. An optimal controller minimizes control errors using a weighted cost functional. The flywheel and control process was tested as a DVR to mitigate voltage sags and swells. Simulation results show that the DVR is able to compensate the critical load voltage without delays, voltage undershoots or overshoots, overcoming the input/output coupling of matrix converters.

On the Problem of Balancing the DC Capacitor Voltage Divider in Back-to-Back Multilevel Converters

This paper presents a new generalized solution for DC bus capacitors voltage balancing in back-to-back m level diode-clamped multilevel converters connecting AC networks. The solution is based on the DC bus average power flow and exploits the switching configuration redundancies. The proposed balancing solution is particularized for the back-to-back multilevel structure with m=5 levels. This back-to-back converter is studied working with bidirectional power flow, connecting an induction machine to the power grid.

Solid-state Marx based two-switch voltage modulator for the On-Line Isotope Mass Separator accelerator at the European Organization for Nuclear Research

A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Repetitive Solid State Pulse Modulator Based on a DC Voltage Multiplier

A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.

Image and color recognition using amorphous silicon p-i-n photodiodes

Large area hydrogenated amorphous silicon single and stacked p-i-n structures with low conductivity doped layers are proposed as monochrome and color image sensors. The layers of the structures are based on amorphous silicon alloys (a-Si(x)C(1-x):H). The current-voltage characteristics and the spectral sensitivity under different bias conditions are analyzed. The output characteristics are evaluated under different read-out voltages and scanner wavelengths. To extract information on image shape, intensity and color, a modulated light beam scans the sensor active area at three appropriate bias voltages and the photoresponse in each scanning position ("sub-pixel") is recorded. The investigation of the sensor output under different scanner wavelengths and varying electrical bias reveals that the response can be tuned, thus enabling color separation. The operation of the sensor is exemplified and supported by a numerical simulation.