Physical layer aware network architecture for the future internet

In this article, physical layer awareness in access, core, and metro networks is addressed, and a Physical Layer Aware Network Architecture Framework for the Future Internet is presented and discussed, as proposed within the framework of the European ICT Project 4WARD. Current limitations and shortcomings of the Internet architecture are driving research trends at a global scale toward a novel, secure, and flexible architecture. This Future Internet architecture must allow for the co-existence and cooperation of multiple networks on common platforms, through the virtualization of network resources. Possible solutions embrace a full range of technologies, from fiber backbones to wireless access networks. The virtualization of physical networking resources will enhance the possibility of handling different profiles, while providing the impression of mutual isolation. This abstraction strategy implies the use of well elaborated mechanisms in order to deal with channel impairments and requirements, in both wireless (access) and optical (core) environments.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

FPGA-based architecture for hyperspectral unmixing

This paper proposes an FPGA-based architecture for onboard hyperspectral unmixing. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral datasets. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems.

FPGA-based architecture for hyperspectral endmember extraction

Hyperspectral instruments have been incorporated in satellite missions, providing data of high spectral resolution of the Earth. This data can be used in remote sensing applications, such as, target detection, hazard prevention, and monitoring oil spills, among others. In most of these applications, one of the requirements of paramount importance is the ability to give real-time or near real-time response. Recently, onboard processing systems have emerged, in order to overcome the huge amount of data to transfer from the satellite to the ground station, and thus, avoiding delays between hyperspectral image acquisition and its interpretation. For this purpose, compact reconfigurable hardware modules, such as field programmable gate arrays (FPGAs) are widely used. This paper proposes a parallel FPGA-based architecture for endmember’s signature extraction. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data sets collected by the NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems, opening new perspectives for onboard hyperspectral image processing.

Le cinéma et la question du Portugal après le 25 avril 1974

O projecto “Principais tendências no cinema português contemporâneo” nasceu no Departamento de Cinema da ESTC, com o objectivo de desenvolver investigação especializada a partir de um núcleo formado por alunos da Licenciatura em Cinema e do Mestrado em Desenvolvimento de Projecto Cinematográfico, a que se juntaram professores-investigadores membros do CIAC e convidados. O que agora se divulga corresponde a dois anos e meio de trabalho desenvolvido pela equipa de investigação, entre Abril de 2009 e Novembro de 2011. Dada a forma que ele foi adquirindo, preferimos renomeá-lo, para efeitos de divulgação, “Novas & velhas tendências no cinema português contemporâneo”.

Stacked photo-sensing devices based on SiC alloys A non-pixelled architecture for imagers and demultiplexing devices

In this review paper different designs based on stacked p-i'-n-p-i-n heterojunctions are presented and compared with the single p-i-n sensing structures. The imagers utilise self-field induced depletion layers for light detection and a modulated laser beam for sequential readout. The effect of the sensing element structure, cell configurations (single or tandem), and light source properties (intensity and wavelength) are correlated with the sensor output characteristics (light-to-dark sensivity, spatial resolution, linearity and S/N ratio). The readout frequency is optimized showing that scans speeds up to 104 lines per second can be achieved without degradation in the resolution. Multilayered p-i'-n-p-i-n heterostructures can also be used as wavelength-division multiplexing /demultiplexing devices in the visible range. Here the sensor element faces the modulated light from different input colour channels, each one with a specific wavelength and bit rate. By reading out the photocurrent at appropriated applied bias, the information is multiplexed or demultiplexed and can be transmitted or recovered again. Electrical models are present to support the sensing methodologies.

A Flexible Architecture for the Computation of Direct and Inverse Transforms in H.264/AVC Video Codecs

A new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of theproposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).

Écrire à l' université: jeux et enjeux didactiques

Nous présentons, dans cette communication, les resultats d'une étude menée dans le cours d'expression orale et écrite dispensé en premier année à l'Escola Superior de Educação de Lisbonne.

Pour une approche contrastive du présent simple en français et en portugais

Les temps du passé ont toujours constitué une pierre d’achoppement aussi bien dans l’enseignement du français aux étudiants lusophones que dans celui du portugais aux francophones. Le flot continu d’articles sur ce sujet attesterait, à lui seul, la difficulté du problème. Mais aussi étonnant que cela puisse paraître, il n’existe à ce jour aucune étude systématique qui aborde sur une base théorique le présent simple dans le passage du français vers le portugais et/ou vice-versa. Or, une telle étude nous paraît une voie de recherche intéressante et fructueuse qui ouvre de nombreuses perspectives de recherche, dont les possibilités d’application, que ce soit au domaine de l’enseignement des langues étrangères ou celui de la traduction, ne sont pas négligeables. Cette réflexion est d’autant plus urgente que l’emploi du présent simple pose de sérieux problèmes aux élèves lusophones plus inexpérimentés. En effet, ces derniers ont parfois beaucoup de peine à trouver les bonnes correspondances du présent simple en portugais. Afin d’aboutir à des conclusions fiables sur les similarités et les divergences entre le français et le portugais quant aux conditions d’apparition et au mode de fonctionnement du présent simple, nous nous attacherons, dans l’étude contrastive qui suit, à examiner des échantillons de textes littéraires français traduits en portugais et des extraits de textes littéraires portugais traduits en français1. Il s’agira essentiellement de montrer, en recourant à la Théorie des Opérations Énonciatives d’Antoine Culioli (Culioli, 1990; Campos & Xavier, 1991; Campos, 1997, 1998, entre autres), par quels moyens linguistiques le portugais exprime les valeurs aspectuo-temporelles associées au présent simple en français.

Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

Pratiques d’enseignement en lecture-écriture et apprentissages des élèves au début du primaire

Esta investigação pretende contribuir para o desenvolvimento da investigação interessada nas questões relativas ao ensino/ aprendizagem do modo escrito nos primeiros anos do primeiro ciclo do ensino básico, particularmente tendo em conta as práticas mais propensas a apoiar a aprendizagem bem-sucedida da leitura e de escrita. Especificamente, esta investigação tem como objetivo descrever as práticas de ensino observadas nas áreas da leitura e da escrita com 22 professores, mas também para relacionar essas práticas observadas com o desempenho em leitura e escrita dos seus alunos do primeiro e do segundo ano. Globalmente, os resultados indicam que as práticas observadas, tanto do ponto de vista dos Dispositivos mobilizados como do conteúdo ensinado, são variadas e contribuem para uma visão complexa da entrada na escrita. As análises de correlação sugerem que determinadas práticas, que geralmente procuram a participação activa das crianças e as interações com os outros, estão relacionados com o progresso dos alunos durante o ano letivo.

Processus interactionnel d’appropriation de la syntaxe et de variantes énonciatives diversifiées, indispensable pour l’accès à l’écrit

A investigação tem posto em evidência a correlação entre desenvolvimento linguístico e aprendizagem da leitura e da escrita. Procuramos, em primeiro lugar, explicar, do ponto de vista da linguística, as relações entre oral e escrita focalizando a linguagem da criança desde as primeiras produções à produção autónoma de variantes sintacticamente diversificadas. De seguida, abordamos a questão da passagem do oral à escrita dando especial atenção ao impacto sobre o funcionamento cognitivo do trabalho de ditado ao adulto. Finalmente, propomos pistas de reflexão sobre modalidades de interacção necessárias à entrada no modo escrito e ao seu percurso de aprendizagem dando conta de resultados de investigação acção e formação com a abordagem «Coup de pouce Langage».

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

A Compact and Scalable RNS Architecture

Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013

Activités d’écriture approchée et entrée dans l’écrit des jeunes enfants: analyse comparative de démarches didactiques en première primaire en france

Nous présentons le suivi d’une cohorte d’élèves, de la grande section (troisième année de maternelle en France -5 ans) à la fin du CE1 (deuxième année de primaire –7/8 ans). La population est constituée d’un groupe contrôle et d’un groupe expérimental pratiquant des séances hebdomadaires d’écriture approchée, observées et filmées à différentes périodes de l’année (octobre, mars et juin). Dans notre contribution, nous analysons les séances filmées en fin de CP (première primaire), dans une perspective essentiellement comparatiste. L’objectif est de décrire la démarche didactique mise en œuvre par les enseignantes lors de séances d’enseignement de l’écriture. L'analyse des productions d'écrit et des verbalisations des élèves nous permet également d'évaluer ces démarches d’enseignement et de caractériser celle qui semble le plus propice au développement de compétences métalinguistiques des apprentis scripteurs