Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

Critérios de projecto de um data centre

Dissertação de Natureza Científica para obtenção do grau de Mestre em Engenharia Civil na Área de Especialização de Edificações

José Manuel Pedroso da Silva: um original criador de ex-libris

A obra como criador de ex-libris do português José Manuel Pedroso da Silva importante investigador e criador de Heráldica.

A realização plástica da heráldica do exército português

É feita uma síntese do trabalho de iluminura de escudos-de-armas destinados ao Exército Português pelos diversos artistas plásticos que integraram o Gabinete de Heráldica do Exército, sendo destacado o importante heraldista José Colaço sendo as iluminuras produzidas alvo de análise relativa à sua qualidade estética.

O gabinete de heráldica do exército e as armas da junta de freguesia da Verderena

É historiada e analisada a criação de armas para a Junta de Freguesia da Verderena a partir da colaboração do Gabinete de Heráldica do Exército e avaliada a intervenção da Secção de Heráldica da Associação dos Arqueólogos Portugueses.

Phase correction for passive radar using targets of opportunity

This paper presents a novel phase correction technique for Passive Radar which uses targets of opportunity present in the target area as references. The proposed methodology is quite simple and enables the use of low cost hardware with independent oscillators for the reference and surveillance channels which can be geographically distributed. © 2014 IEEE.

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

Virtual laboratory for educational environments

In this paper a new simulation environment for a virtual laboratory to educational proposes is presented. The Logisim platform was adopted as the base digital simulation tool, since it has a modular implementation in Java. All the hardware devices used in the laboratory course was designed as components accessible by the simulation tool, and integrated as a library. Moreover, this new library allows the user to access an external interface. This work was motivated by the needed to achieve better learning times on co-design projects, based on hardware and software implementations, and to reduce the laboratory time, decreasing the operational costs of engineer teaching. Furthermore, the use of virtual laboratories in educational environments allows the students to perform functional tests, before they went to a real laboratory. Moreover, these functional tests allow to speed-up the learning when a problem based approach methodology is considered. © 2014 IEEE.

Detection and diagnosis solutions for fault-tolerant VSI

This paper presents solutions for fault detection and diagnosis of two-level, three phase voltage-source inverter (VSI) topologies with IGBT devices. The proposed solutions combine redundant standby VSI structures and contactors (or relays) to improve the fault-tolerant capabilities of power electronics in applications with safety requirements. The suitable combination of these elements gives the inverter the ability to maintain energy processing in the occurrence of several failure modes, including short-circuit in IGBT devices, thus extending its reliability and availability. A survey of previously developed fault-tolerant VSI structures and several aspects of failure modes, detection and isolation mechanisms within VSI is first discussed. Hardware solutions for the protection of power semiconductors with fault detection and diagnosis mechanisms are then proposed to provide conditions to isolate and replace damaged power devices (or branches) in real time. Experimental results from a prototype are included to validate the proposed solutions.

Linear and sliding-mode control design for matrix converter-based unified power flow controllers

This paper presents the design and compares the performance of linear, decoupled and direct power controllers (DPC) for three-phase matrix converters operating as unified power flow controllers (UPFC). A simplified steady-state model of the matrix converter-based UPFC fitted with a modified Venturini high-frequency pulse width modulator is first used to design the linear controllers for the transmission line active (P) and reactive (Q) powers. In order to minimize the resulting cross coupling between P and Q power controllers, decoupled linear controllers (DLC) are synthesized using inverse dynamics linearization. DPC are then developed using sliding-mode control techniques, in order to guarantee both robustness and decoupled control. The designed P and Q power controllers are compared using simulations and experimental results. Linear controllers show acceptable steady-state behaviour but still exhibit coupling between P and Q powers in transient operation. DLC are free from cross coupling but are parameter sensitive. Results obtained by DPC show decoupled power control with zero error tracking and faster responses with no overshoot and no steady-state error. All the designed controllers were implemented using the same digital signal processing hardware.

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

A high-rate mimo receiver in an FPGA

This paper describes the hardware implementation of a High-Rate MIMO Receiver in an FPGA for three modulations, namely BPSK, QPSK and 16-QAM based on the Alamouti scheme. The implementation with 16-QAM achieves more than 1.6 Gbps with 66% of the resources of a medium-sized Virtex-4 FPGA. This results indicate that the Alamouti scheme is a good design option for hardware implementation of a high-rate MIMO receiver. Also, using an FPGA, the modulation can be dynamically changed on demand.

FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

A importância do desenho infantil no jardim de infância: perspetiva de pais e de educadoras de infância

Relatório da Prática Profissional Supervisionada Mestrado em Educação Pré-Escolar

Análise técnica aplicada aos mercados cambiais estudo comparativo das cotações EUR/USD, GBP/USD E JPY/USD

Mestrado em Contabilidade e Análise Financeira