Virtual laboratory for educational environments

In this paper a new simulation environment for a virtual laboratory to educational proposes is presented. The Logisim platform was adopted as the base digital simulation tool, since it has a modular implementation in Java. All the hardware devices used in the laboratory course was designed as components accessible by the simulation tool, and integrated as a library. Moreover, this new library allows the user to access an external interface. This work was motivated by the needed to achieve better learning times on co-design projects, based on hardware and software implementations, and to reduce the laboratory time, decreasing the operational costs of engineer teaching. Furthermore, the use of virtual laboratories in educational environments allows the students to perform functional tests, before they went to a real laboratory. Moreover, these functional tests allow to speed-up the learning when a problem based approach methodology is considered. © 2014 IEEE.

Detection and diagnosis solutions for fault-tolerant VSI

This paper presents solutions for fault detection and diagnosis of two-level, three phase voltage-source inverter (VSI) topologies with IGBT devices. The proposed solutions combine redundant standby VSI structures and contactors (or relays) to improve the fault-tolerant capabilities of power electronics in applications with safety requirements. The suitable combination of these elements gives the inverter the ability to maintain energy processing in the occurrence of several failure modes, including short-circuit in IGBT devices, thus extending its reliability and availability. A survey of previously developed fault-tolerant VSI structures and several aspects of failure modes, detection and isolation mechanisms within VSI is first discussed. Hardware solutions for the protection of power semiconductors with fault detection and diagnosis mechanisms are then proposed to provide conditions to isolate and replace damaged power devices (or branches) in real time. Experimental results from a prototype are included to validate the proposed solutions.

Linear and sliding-mode control design for matrix converter-based unified power flow controllers

This paper presents the design and compares the performance of linear, decoupled and direct power controllers (DPC) for three-phase matrix converters operating as unified power flow controllers (UPFC). A simplified steady-state model of the matrix converter-based UPFC fitted with a modified Venturini high-frequency pulse width modulator is first used to design the linear controllers for the transmission line active (P) and reactive (Q) powers. In order to minimize the resulting cross coupling between P and Q power controllers, decoupled linear controllers (DLC) are synthesized using inverse dynamics linearization. DPC are then developed using sliding-mode control techniques, in order to guarantee both robustness and decoupled control. The designed P and Q power controllers are compared using simulations and experimental results. Linear controllers show acceptable steady-state behaviour but still exhibit coupling between P and Q powers in transient operation. DLC are free from cross coupling but are parameter sensitive. Results obtained by DPC show decoupled power control with zero error tracking and faster responses with no overshoot and no steady-state error. All the designed controllers were implemented using the same digital signal processing hardware.

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

A high-rate mimo receiver in an FPGA

This paper describes the hardware implementation of a High-Rate MIMO Receiver in an FPGA for three modulations, namely BPSK, QPSK and 16-QAM based on the Alamouti scheme. The implementation with 16-QAM achieves more than 1.6 Gbps with 66% of the resources of a medium-sized Virtex-4 FPGA. This results indicate that the Alamouti scheme is a good design option for hardware implementation of a high-rate MIMO receiver. Also, using an FPGA, the modulation can be dynamically changed on demand.

FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

Estudo e desenvolvimento de sistema de cobrança de portagens baseado em NFC

Tese para obter o grau de Mestre em Engenharia Electrónica e Telecomunicações

ALS-Sence: sistema de aquisição e processamento de electromiogramas para pacientes com ALS

Dissertação para obtenção do grau de Mestre em Engenharia de Eletrónica e Computadores

Encenação digital: dissertação

Dissertação submetida à Escola Superior de Teatro e Cinema para cumprimento dos requisitos necessários à obtenção do grau de Mestre em Teatro - especialização em Encenação.

Controlo de conversores de potência genéricos por FPGA

Dissertação para obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e Eletrónica Industrial

Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA

Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution.

Parallel GPU architecture for hyperspectral unmixing based on augmented Lagrangian method

Hyperspectral imaging has become one of the main topics in remote sensing applications, which comprise hundreds of spectral bands at different (almost contiguous) wavelength channels over the same area generating large data volumes comprising several GBs per flight. This high spectral resolution can be used for object detection and for discriminate between different objects based on their spectral characteristics. One of the main problems involved in hyperspectral analysis is the presence of mixed pixels, which arise when the spacial resolution of the sensor is not able to separate spectrally distinct materials. Spectral unmixing is one of the most important task for hyperspectral data exploitation. However, the unmixing algorithms can be computationally very expensive, and even high power consuming, which compromises the use in applications under on-board constraints. In recent years, graphics processing units (GPUs) have evolved into highly parallel and programmable systems. Specifically, several hyperspectral imaging algorithms have shown to be able to benefit from this hardware taking advantage of the extremely high floating-point processing performance, compact size, huge memory bandwidth, and relatively low cost of these units, which make them appealing for onboard data processing. In this paper, we propose a parallel implementation of an augmented Lagragian based method for unsupervised hyperspectral linear unmixing on GPUs using CUDA. The method called simplex identification via split augmented Lagrangian (SISAL) aims to identify the endmembers of a scene, i.e., is able to unmix hyperspectral data sets in which the pure pixel assumption is violated. The efficient implementation of SISAL method presented in this work exploits the GPU architecture at low level, using shared memory and coalesced accesses to memory.

Parallel hyperspectral coded aperture for compressive sensing on GPUs

The application of compressive sensing (CS) to hyperspectral images is an active area of research over the past few years, both in terms of the hardware and the signal processing algorithms. However, CS algorithms can be computationally very expensive due to the extremely large volumes of data collected by imaging spectrometers, a fact that compromises their use in applications under real-time constraints. This paper proposes four efficient implementations of hyperspectral coded aperture (HYCA) for CS, two of them termed P-HYCA and P-HYCA-FAST and two additional implementations for its constrained version (CHYCA), termed P-CHYCA and P-CHYCA-FAST on commodity graphics processing units (GPUs). HYCA algorithm exploits the high correlation existing among the spectral bands of the hyperspectral data sets and the generally low number of endmembers needed to explain the data, which largely reduces the number of measurements necessary to correctly reconstruct the original data. The proposed P-HYCA and P-CHYCA implementations have been developed using the compute unified device architecture (CUDA) and the cuFFT library. Moreover, this library has been replaced by a fast iterative method in the P-HYCA-FAST and P-CHYCA-FAST implementations that leads to very significant speedup factors in order to achieve real-time requirements. The proposed algorithms are evaluated not only in terms of reconstruction error for different compressions ratios but also in terms of computational performance using two different GPU architectures by NVIDIA: 1) GeForce GTX 590; and 2) GeForce GTX TITAN. Experiments are conducted using both simulated and real data revealing considerable acceleration factors and obtaining good results in the task of compressing remotely sensed hyperspectral data sets.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

Sistema localizador interior de baixo custo

Projeto para obtenção do grau de Mestre em Engenharia Informática e de Computadores