The impact of the 2008 and 2010 financial crises on international stock markets : contagion and long memory

Nesta tese estudamos os efeitos de contágio financeiro e de memória longa causados pelas crises financeiras de 2008 e 2010 em alguns mercados acionistas internacionais. A tese é composta por três ensaios interligados. No Ensaio 1, recorremos à teoria das cópulas para testar a existência de contágio e revelar os canais “investor induced” de transmissão da crise de 2008 aos mercados da Bélgica, França, Holanda e Portugal (grupo NYSE Euronext). Concluímos que existe contágio nestes mercados, que o canal “portfolio rebalancing” é o mecanismo mais importante de transmissão da crise, e que o fenómeno “flight to quality” está presente nos mercados. No Ensaio 2, usando novamente modelos de cópulas, avaliamos os efeitos de contágio provocados pelo mercado acionista grego nos mercados do grupo NYSE Euronext, no contexto da crise de 2010. Os resultados obtidos sugerem que durante a crise de 2010 apenas o mercado português foi objeto de contágio; além disso, conclui-se que os efeitos de contágio provocados pela crise de 2008 são claramente superiores aos efeitos provocados pela crise de 2010. No Ensaio 3, abordamos o tema da memória longa através do estudo do expoente de Hurst dos mercados acionistas da Bélgica, E.U.A., França, Grécia, Holanda, Japão, Reino Unido e Portugal. Verificamos que as propriedades de memória longa dos mercados foram afetadas pelas crises, especialmente a de 2008 – que aumentou a memória longa dos mercados e tornou-os mais persistentes. Finalmente, usando cópulas mais uma vez, verificamos que as crises provocaram, em geral, um aumento na correlação entre os expoentes de Hurst locais dos mercados foco das crises (E.U.A. e Grécia) e os expoentes de Hurst locais dos outros mercados da amostra, sugerindo que o expoente de Hurst pode ser utilizado para detetar efeitos de contágio financeiro. Em síntese, os resultados desta tese sugerem que comparativamente com períodos de acalmia, os períodos de crises financeiras tendem a provocar ineficiência nos mercados acionistas e a conduzi-los na direção da persistência e do contágio financeiro.

Light memory function in a double pin SiC device

A double pi'npin heterostructure based on amorphous SiC has a non linear spectral gain which is a function of the signal wavelength that impinges on its front or back surface. An impulse of a configurable length and amplitude is applied to a 390 nm LED which illuminates one of the sensor surfaces, followed by a time period without any illumination after which an input signal with a different wavelength is impinged upon the front surface. Results show that the intensity and duration of the impulse illumination of the surfaces influences the sensor's response with different output for the same input signal. This paper studies this effect and proposes an application as a short term light memory. (C) 2015 Elsevier B.V. All rights reserved.

Controlo de conversores de potência genéricos por FPGA

Dissertação para obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e Eletrónica Industrial

Optimizing memory transactions for large-scale programs

Even though Software Transactional Memory (STM) is one of the most promising approaches to simplify concurrent programming, current STM implementations incur significant overheads that render them impractical for many real-sized programs. The key insight of this work is that we do not need to use the same costly barriers for all the memory managed by a real-sized application, if only a small fraction of the memory is under contention lightweight barriers may be used in this case. In this work, we propose a new solution based on an approach of adaptive object metadata (AOM) to promote the use of a fast path to access objects that are not under contention. We show that this approach is able to make the performance of an STM competitive with the best fine-grained lock-based approaches in some of the more challenging benchmarks. (C) 2015 Elsevier Inc. All rights reserved.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA

Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution.

FPGA-based architecture for hyperspectral unmixing

This paper proposes an FPGA-based architecture for onboard hyperspectral unmixing. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral datasets. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems.

Light memory operation based on a double pin SiC device

Experimental optoelectronic characterization of a p-i'(a-SiC:H)-n/pi(a-Si:H)-n heterostructure with low conductivity doped layers shows the feasibility of tailoring channel bandwidth and wavelength by optical bias through back and front side illumination. Front background enhances light-to-dark sensitivity of the long and medium wavelength range, and strongly quenches the others. Back violet background enhances the magnitude in short wavelength range and reduces the others. Experiments have three distinct programmed time slots: control, hibernation and data. Throughout the control time slot steady light wavelengths illuminate either or both sides of the device, followed by the hibernation without any background illumination. The third time slot allows a programmable sequence of different wavelengths with an impulse frequency of 6000Hz to shine upon the sensor. Results show that the control time slot illumination has an influence on the data time slot which is used as a volatile memory with the set, reset logical functions. © IFIP International Federation for Information Processing 2015.