Comparison between DC(+) and Square Wave AC SAW Current Outputs to Weld AISI 304 for Low-Temperature Applications

Welded equipment for cryogenic applications is utilized in chemical, petrochemical, and metallurgical industries. One material suitable for cryogenic application is austenitic stainless steel, which usually doesn`t present ductile/brittle transition temperature, except in the weld metal, where the presence of ferrite and micro inclusions can promote a brittle failure, either by ferrite cleavage or dimple nucleation and growth, respectively. A 25-mm- (1-in.-) thick AISI 304 stainless steel base metal was welded with the SAW process using a 308L solid wire and two kinds of fluxes and constant voltage power sources with two types of electrical outputs: direct current electrode positive and balanced square wave alternating current. The welded joints were analyzed by chemical composition, microstructure characterization, room temperature mechanical properties, and CVN impact test at -100 degrees C (-73 degrees F). Results showed that an increase of chromium and nickel content was observed in all weld beads compared to base metal. The chromium and nickel equivalents ratio for the weld beads were always higher for welding with square wave AC for the two types of fluxes than for direct current. The modification in the Cr(eq)/Ni(eq) ratio changes the delta ferrite morphology and, consequently, modifies the weld bead toughness at lower temperatures. The oxygen content can also affect the toughness in the weld bead. The highest absorbed energy in a CVN impact test was obtained for the welding condition with square wave AC electrical output and neutral flux, followed by DC(+) electrical output and neutral flux, and square wave AC electrical output and alloyed flux.

Impact of plastic deformation on magnetoacoustic properties of Fe-2%Si alloy

The paper presents the results of a complementary study including magnetic hysteresis loops B(H), magnetic Barkhausen noise (MBN) and magnetoacoustic emission (MAE) signals measurements for plastically deformed Fe-2%Si samples. The investigated samples had been plastically deformed with plastic strain level (epsilon(p)) up to 8%. The properties of B(H) loops are quantified using the coercivity H(C) and maximum differential permeability mu(rmax) as parameters. The MBN and MAE voltage signals were analysed by means of rms-like voltage (Ub and Ua, respectively) envelopes, plotted as a function of applied field strength. Integrals of the Ub and Ua voltages over half of a period of magnetization were then calculated. It has been found that He and integrals of Ub increase, while mu(rmax) decreases monotonically with increasing epsilon(p). The MAE (Ua) peak voltage at first decreases, then peaks at epsilon(p) approximate to 1.5% and finally decreases again. The integral of the Ua voltage at first increases for low epsilon(p) and then decreases for epsilon(p) > 1.5%. All those various dependence types suggest the possibility of detection of various stages of microstructure change. The above-mentioned results are discussed qualitatively in the paper. Some modelling of the discussed dependency is also presented. (C) 2008 Elsevier Ltd. All rights reserved.

An In-Depth Study of the Barkhausen Emission Signal Properties of the Plastically Deformed Fe-2%Si Alloy

This paper presents the results of the in-depth study of the Barkhausen effect signal properties for the plastically deformed Fe-2%Si samples. The investigated samples have been deformed by cold rolling up to plastic strain epsilon(p) = 8%. The first approach consisted of time-domain-resolved pulse and frequency analysis of the Barkhausen noise signals whereas the complementary study consisted of the time-resolved pulse count analysis as well as a total pulse count. The latter included determination of time distribution of pulses for different threshold voltage levels as well as the total pulse count as a function of both the amplitude and the duration time of the pulses. The obtained results suggest that the observed increase in the Barkhausen noise signal intensity as a function of deformation level is mainly due to the increase in the number of bigger pulses.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Open-circuit voltages: Theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers

The theoretical and experimental open-circuit voltage optimizations of a simple fabrication process of silicon solar cells n(+)p with rear passivation are presented. The theoretical results were obtained by using an in-house developed program, including the light trapping effect and metal-grid optimization. On the other hand, the experimental steps were monitored by the photoconductive decay technique. The starting materials presented thickness of about 300 pm and resistivities: FZ (0.5 Omega cm), Cz-type 1 (2.5 Omega cm) and Cz-type 2 (3.3 Omega cm). The Gaussian profile emitters were optimized with sheet resistance between 55 Omega/sq and 100 Omega/sq, and approximately 2.0 mu m thickness in accordance to the theoretical results. Excellent implied open-circuit voltages of 670.8 mV, 652.5 mV and 662.6 mV, for FZ, Cz-type 1 and Cz-type 2 silicon wafers, respectively, could be associated to the measured lifetimes that represents solar cell efficiency up to 20% if a low cost anti-reflection coating system, composed by random pyramids and SiO(2) layer, is considered even for typical Cz silicon. (C) 2009 Elsevier Ltd. All rights reserved.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Probing Individual Quantum Dots: Noise in Self-Assembled Systems

In this work we explore the noise characteristics in lithographically-defined two terminal devices containing self-assembled InAs/InP quantum dots. The experimental ensemble of InAs dots show random telegraph noise (RTN) with tuneable relative amplitude-up to 150%-in well defined temperature and source-drain applied voltage ranges. Our numerical simulation indicates that the RTN signature correlates with a very low number of quantum dots acting as effective charge storage centres in the structure for a given applied voltage. The modulation in relative amplitude variation can thus be associated to the altered electrostatic potential profile around such centres and enhanced carrier scattering provided by a charged dot.

Cryogenic operation of FinFETs aiming at analog applications

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. (C) 2009 Elsevier Ltd. All rights reserved.

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO(x)) dielectric layer, deposited with different oxygen partial pressure (30,35 and 40%) and annealed at 550, 750 and 1000 degrees C, were fabricated and characterized. Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of - 1 V, as low as 1 nA/cm(2) for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers. (C) 2009 Elsevier B.V. All rights reserved.

Low-temperature deposition of silicon oxide and silicon nitride by reactive magnetron sputtering

In this study, oxide and nitride films were deposited at room temperature through the reaction of silicon Sputtered by argon and oxygen ions or argon and nitrogen ions at 250 and 350 W with 0.67 Pa pressure. It was observed that for both thin films the deposition rates increase with the applied RF power and decrease with the increase of the gas concentration. The Si/O and Si/N ratio were obtained through RBS analyses and for silicon oxide the values changed from 0.42 to 0.57 and for silicon nitride the Values changed from 0.4 to 1.03. The dielectric constants were calculated through capacitance-voltage curves with the silicon oxide values varying from 2.4 to 5.5, and silicon nitride values varying from 6.2 to 6.7, which are good options for microelectronic dielectrics. (c) 2008 Elsevier Ltd. All rights reserved.

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.