Characterization of complex quantum dynamics with a scalable NMR information processor

We present experimental results on the measurement of fidelity decay under contrasting system dynamics using a nuclear magnetic resonance quantum information processor. The measurements were performed by implementing a scalable circuit in the model of deterministic quantum computation with only one quantum bit. The results show measurable differences between regular and complex behavior and for complex dynamics are faithful to the expected theoretical decay rate. Moreover, we illustrate how the experimental method can be seen as an efficient way for either extracting coarse-grained information about the dynamics of a large system or measuring the decoherence rate from engineered environments.

Functionally partitioned module-based programmable architecture for wireless base-band processing

A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included. This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced. The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

Managing woodlands for income maximisation in western Queensland, Australia: clearing for grazing versus timber production

Queensland, Australia, has a proud pastoral history; however, the private and social benefits of continued woodland clearing for pasture development are unlikely to be as pronounced as they had been in the past. The environmental benefits of tree retention in and regions of the State are now better appreciated and market opportunities have arisen for the unique timbers of western Queensland. A financial model is developed to facilitate a comparison of the private profitability of small-scale timber production from remnant Acacia woodlands against clearing for pasture development in the Mulga Lands and Desert Uplands bioregions of western Queensland. Four small-scale timber production scenarios, which differ in target markets and the extent of processing (value-adding), are explored within the model. Each scenario is examined for the cases where property rights to the timber are vested with the timber processor, and where royalties are payable. For both cases of resource ownership, at least one scenario generates positive returns from timber production, and exceeds the net farm income per hectare for an average grazing property in the study regions over the period 1989-1990 to 2000-2001. The net present value per hectare of selectively harvesting and processing high-value clearwood from remnant western Queensland woodlands is found to be greater than clearing for grazing. (C) 2003 Elsevier B.V. All rights reserved.

Design and implementation of a windows-based parallel computing environment for large scale optimization

A parallel computing environment to support optimization of large-scale engineering systems is designed and implemented on Windows-based personal computer networks, using the master-worker model and the Parallel Virtual Machine (PVM). It is involved in decomposition of a large engineering system into a number of smaller subsystems optimized in parallel on worker nodes and coordination of subsystem optimization results on the master node. The environment consists of six functional modules, i.e. the master control, the optimization model generator, the optimizer, the data manager, the monitor, and the post processor. Object-oriented design of these modules is presented. The environment supports steps from the generation of optimization models to the solution and the visualization on networks of computers. User-friendly graphical interfaces make it easy to define the problem, and monitor and steer the optimization process. It has been verified by an example of a large space truss optimization. (C) 2004 Elsevier Ltd. All rights reserved.

Formal change impact analyses for emulated control software

Processor emulators are a software tool for allowing legacy computer programs to be executed on a modern processor. In the past emulators have been used in trivial applications such as maintenance of video games. Now, however, processor emulation is being applied to safety-critical control systems, including military avionics. These applications demand utmost guarantees of correctness, but no verification techniques exist for proving that an emulated system preserves the original system’s functional and timing properties. Here we show how this can be done by combining concepts previously used for reasoning about real-time program compilation, coupled with an understanding of the new and old software architectures. In particular, we show how both the old and new systems can be given a common semantics, thus allowing their behaviours to be compared directly.

Wills' mineral processing technology: an introduction to the practical aspects of ore treatment and mineral recovery

"Wills' Mineral Processing Technology" provides practising engineers and students of mineral processing, metallurgy and mining with a review of all of the common ore-processing techniques utilized in modern processing installations. Now in its Seventh Edition, this renowned book is a standard reference for the mineral processing industry. Chapters deal with each of the major processing techniques, and coverage includes the latest technical developments in the processing of increasingly complex refractory ores, new equipment and process routes. This new edition has been prepared by the prestigious J K Minerals Research Centre of Australia, which contributes its world-class expertise and ensures that this will continue to be the book of choice for professionals and students in this field. This latest edition highlights the developments and the challenges facing the mineral processor, particularly with regard to the environmental problems posed in improving the efficiency of the existing processes and also in dealing with the waste created. The work is fully indexed and referenced. -The classic mineral processing text, revised and updated by a prestigious new team -Provides a clear exposition of the principles and practice of mineral processing, with examples taken from practice -Covers the latest technological developments and highlights the challenges facing the mineral processor -New sections on environmental problems, improving the efficiency of existing processes and dealing with waste.

Interface adaptor logic: A new model for interfacing peripherals in IP based designs

The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.