An FPGA network architecture for accelerating 3DES - CBC

This paper presents a DES/3DES core that will support cipher block chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.

Assessing an FPGA implemented MIMO testbed with the use of channel emulator

In this paper, a channel emulator for assessing the performance of MIMO testbed implemented in a field programmable gate array technology is described. The FPGA based MIMO system includes a signal generator, modulation/demodulation and space time coding/decoding modules. The emulator uses information about a wireless channel from computer simulations or actual measurements. In simulations, a single bounce scattering model for an indoor environment is applied. The generated data is stored in the FPGA board. The tests are performed for a 2times2 MIMO system that uses Alamouti scheme for space coding/decoding. The performed tests show proper operation of the FPGA implemented MIMO testbed. Good agreement between the results using measured and simulated channel data is obtained.

Design of MIMO testbed with an FPGA board for fast signal processing

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

Implementation of a triple modular redundant FPGA based safety critical system for reliable software execution

This paper describes the implementation of a TMR (Triple Modular Redundant) microprocessor system on a FPGA. The system exhibits true redundancy in that three instances of the same processor system (both software and hardware) are executed in parallel. The described system uses software to control external peripherals and a voter is used to output correct results. An error indication is asserted whenever two of the three outputs match or all three outputs disagree. The software has been implemented to conform to a particular safety critical coding guideline/standard which is popular in industry. The system was verified by injecting various faults into it.