30 resultados para high-level synthesis
Resumo:
The transfer ionization process offers a unique opportunity to study radial and angular electron correlations in the helium atom. We report calculations for the multiple differential cross sections of the transfer ionization process p + He --> H + He++ + e(-). The results of these calculations demonstrate the strong sensitivity of the fully differential cross sections to fine details of electron correlation in the target atom. Specifically, angular electron correlation in the ground state of helium results in a broad peak in the electron emission spectra in the backward direction, relative to the incoming beam. Our model explains some of the key effects observed in measurements of multiple differential cross sections using the COLTRIMS technique.
The use of high level tools for developing volume graphic and video sequence processing applications
Resumo:
For modern FPGA, implementation of memory intensive processing applications such as high end image and video processing systems necessitates manual design of complex multilevel memory hierarchies incorporating off-chip DDR and onchip BRAM and LUT RAM. In fact, automated synthesis of multi-level memory hierarchies is an open problem facing high level synthesis technologies for FPGA devices. In this paper we describe the first automated solution to this problem.
By exploiting a novel dataflow application modelling dialect, known as Valved Dataflow, we show for the first time how, not only can such architectures be automatically derived, but also that the resulting implementations support real-time processing for current image processing application standards such as H.264. We demonstrate the viability of this approach by reporting the performance and cost of hierarchies automatically generated for Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications on Virtex-5 FPGA.
Resumo:
A simple, non-seeding and high-yield synthesis of convex gold octahedra with size of ca. 50 nm in aqueous solution is described. The octahedral nanoparticles were systematically prepared by reduction of HAuCl4 using ascorbic acid (AA) in the presence of cetyltrimethylammonium bromide (CTAB) as the stabilizing surfactant while concentrations of Au3+ were fixed. The synthesizing process is especially different to other wet synthesis of metallic nanoparticles because it is mediated by H2O2. Mechanism of the H2O2 – mediated process will be described in details. The gold octahedra were shown to be single crystals with all 8 faces belonging to {111} family. Moreover, the single crystalline particles also showed attractive optical properties towards LSPR that should find uses as labels for microscopic imaging, materials for colorimetric biosensings, or nanosensor developments.
Resumo:
Mechanisms of antibiotic resistance were examined in nalidixic acid-resistant Salmonella enterica serovar Enteritidis field isolates displaying decreased susceptibility to ciprofloxacin and in in vitro-derived ciprofloxacin-resistant mutants (104-cip and 5408-cip). All field isolates harbored a single gyrA mutation (D87Y). Deletion of acrB and complementation with wild-type gyrA increased quinolone susceptibility. Selection for ciprofloxacin resistance was associated with the development of an additional gyrA (S83F) mutation in 104-cip, novel gyrB (E466D) and parE (V461G) mutations in 5408-cip, overexpression of acrB and decreased susceptibility to nonquinolone antibiotics in both mutants, and decreased OmpF production and altered lipopoly- saccharide in 104-cip. Complementation of mutated gyrA and gyrB with wild-type alleles restored susceptibility to quinolones in 104-cip and significantly decreased the ciprofloxacin MIC in 5408-cip. Complementation of parE had no effect on quinolone MICs. Deletion of acrB restored susceptibility to ciprofloxacin and other antibiotics tested. Both soxS and marA were overexpressed in 104-cip, and ramA was overexpressed in 5408-cip. Inactivation of each of these global regulators lowered ciprofloxacin MICs, decreased expression of acrB, and restored susceptibility to other antibiotics. Mutations were found in soxR (R20H) and in soxS (E52K) in 104-cip and in ramR (G25A) in 5408-cip. In conclusion, both efflux activity and a single gyrA mutation contribute to nalidixic acid resistance and reduced ciprofloxacin sensitivity. Ciprofloxacin resistance and decreased susceptibility to multiple antibiotics can result from different genetic events leading to development of target gene mutations, increased efflux activity resulting from differential expression of global regulators associated with mutations in their regulatory genes, and possible altered membrane permeability.
Resumo:
This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demon- strates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.
Resumo:
Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but de- mand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple ap- proaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estima- tion, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, op- timizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.