Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures


Autoria(s): Papagiannis, Anastasios; Nikolopoulos, Dimitrios
Data(s)

01/11/2014

Resumo

This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demon- strates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.

Formato

application/pdf

Identificador

http://pure.qub.ac.uk/portal/en/publications/hybrid-address-spaces-a-methodology-for-implementing-scalable-highlevel-programming-models-on-noncoherent-manycore-architectures(76c58d97-f89e-4b54-9afa-8c633981ae81).html

http://dx.doi.org/10.1016/j.jss.2014.06.058

http://pure.qub.ac.uk/ws/files/10504524/paper.pdf

Idioma(s)

eng

Direitos

info:eu-repo/semantics/restrictedAccess

Fonte

Papagiannis , A & Nikolopoulos , D 2014 , ' Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures ' Journal of Systems and Software , vol 97 , pp. 47-64 . DOI: 10.1016/j.jss.2014.06.058

Tipo

article