Light emission from gold and silver thin films in a scanning tunneling microscope: role of contamination and interpretation of grain structure in photon maps

Scanning tunnelling microscope (STM) tip-induced light emission from Au and Ag has been studied. Thin film samples similar to100nm thick were prepared by thermal evaporation at 0.5nm/s onto a room-temperature glass substrate to produce grains of 20-50nm in lateral dimension at the surface. Light emission from the samples in the STM was quasi-simultaneously recorded with the topography, at 1.8V tip bias and 3-40nA current, alternating pixel by pixel at the same bias. Typically, a surface scan range of 150 nm x 150 nm was surveyed. Au, W and PtIr tips were used.

ALEA: Fine-Grain Energy Profiling with Basic Block Sampling

Energy efficiency is an essential requirement for all contemporary computing systems. We thus need tools to measure the energy consumption of computing systems and to understand how workloads affect it. Significant recent research effort has targeted direct power measurements on production computing systems using on-board sensors or external instruments. These direct methods have in turn guided studies of software techniques to reduce energy consumption via workload allocation and scaling. Unfortunately, direct energy measurements are hampered by the low power sampling frequency of power sensors. The coarse granularity of power sensing limits our understanding of how power is allocated in systems and our ability to optimize energy efficiency via workload allocation.
We present ALEA, a tool to measure power and energy consumption at the granularity of basic blocks, using a probabilistic approach. ALEA provides fine-grained energy profiling via sta- tistical sampling, which overcomes the limitations of power sens- ing instruments. Compared to state-of-the-art energy measurement tools, ALEA provides finer granularity without sacrificing accuracy. ALEA achieves low overhead energy measurements with mean error rates between 1.4% and 3.5% in 14 sequential and paral- lel benchmarks tested on both Intel and ARM platforms. The sampling method caps execution time overhead at approximately 1%. ALEA is thus suitable for online energy monitoring and optimization. Finally, ALEA is a user-space tool with a portable, machine-independent sampling method. We demonstrate two use cases of ALEA, where we reduce the energy consumption of a k-means computational kernel by 37% and an ocean modelling code by 33%, compared to high-performance execution baselines, by varying the power optimization strategy between basic blocks.

A design strategy of large grain lithium-rich layered oxides for lithium-ion batteries cathode

Li-rich materials are considered the most promising for Li-ion battery cathodes, as high capacity can be achieved. However, poor cycling stability is a critical drawback that leads to poor capacity retention. Here a strategy is used to synthesize a large-grain lithium-rich layered oxides to overcome this difficulty without sacrificing rate capability. This material is designed with micron scale grain with a width of about 300 nm and length of 1-3 μm. This unique structure has a better ability to overcome stress-induced structural collapse caused by Li-ion insertion/extraction and reduce the dissolution of Mn ions, which enable a reversible and stable capacity. As a result, this cathode material delivered a highest discharge capacity of around 308 mAh g^-1 at a current density of 30 mA g^-1 with retention of 88.3% (according to the highest discharge capacity) after 100 cycles, 190 mAh g^-1 at a current density of 300 mA g^-1 and almost no capacity fading after 100 cycles. Therefore, Lithium-rich material of large-grain structure is a promising cathode candidate in Lithium-ion batteries with high capacity and high cycle stability for application. This strategy of large grain may furthermore open the door to synthesize the other complex architectures for various applications.

MHD Wave Modes Resolved in Fine-Scale Chromospheric Magnetic Structures

Due to its complex and dynamic fine-scale structure, the chromosphere is a particularly challenging region of the Sun's atmosphere to understand. It is now widely accepted that to model chromospheric dynamics, even on a magnetohydrodynamic (MHD) scale, while also calculating spectral line emission, one must realistically include the effects of partial ionization and radiative transfer in a multi-fluid plasma under non-LTE conditions. Accurate quantification of MHD wave energetics must befounded on a precise identification of the actual wave mode being observed. This chapter focuses on MHD kink-mode identification, MHD sausage mode identification, and MHD torsional Alfvén wave identification. It then reviews progress in determining more accurate energy flux estimations of specific MHD wave modes observed in the chromosphere. The chapter finally examines how the discovery of these MHD wave modes has helped us advance the field of chromosphericmagnetoseismology.

Germanium bonding to AI2O3

Germanium has been bonded to both single crystal Al2O 3 (sapphire) as well as fine grain Al2O3. A germanium to sapphire bonding energy of 3 J/m2 has been measured after a 200 °C bond anneal. Micro voids formed between the germanium/sapphire interface can be removed by employing an interfacial layer of silicon dioxide on either surface. Patterning the sapphire into a grid pattern prior to bonding creates an escape path for trapped gas or moisture allowing micro void free direct bonding to be achieved. Modifying the surface of the fine grain Al2O3 surface with a polycrystalline silicon deposition and polish creates a surface, having an rms roughness (measured over a 250© m2 area), of 1.5nm, suitable for bonding. Techniques employed in the germanium sapphire bonding can then be used in the bonding of fine grain A12O3 to germanium. © The Electrochemical Society.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Pipelined two-port adaptor for wave digital filtering

The application of fine-grain pipelining techniques in the design of high-performance wave digital filters (WDFs) is described. The problems of latency in feedback loops can be significantly reduced if computations are organized most significant, as opposed to least significant, bit first and if the results are fed back as soon as they are formed. The result is that chips can be designed which offer significantly higher sampling rates than otherwise can be obtained using conventional methods. How these concepts can be extended to the more challenging problem of WDFs is discussed. It is shown that significant increases in the sampling rate of bit-parallel circuits can be achieved using most significant bit first arithmetic.

Targeting distributed systems in FastFlow

FastFlow is a structured parallel programming framework targeting shared memory multi-core architectures. In this paper we introduce a FastFlow extension aimed at supporting also a network of multi-core workstations. The extension supports the execution of FastFlow programs by coordinating-in a structured way-the fine grain parallel activities running on a single workstation. We discuss the design and the implementation of this extension presenting preliminary experimental results validating it on state-of-the-art networked multi-core nodes. © 2013 Springer-Verlag.

An efficient unbounded lock-free queue for multi-core systems

The use of efficient synchronization mechanisms is crucial for implementing fine grained parallel programs on modern shared cache multi-core architectures. In this paper we study this problem by considering Single-Producer/Single- Consumer (SPSC) coordination using unbounded queues. A novel unbounded SPSC algorithm capable of reducing the row synchronization latency and speeding up Producer-Consumer coordination is presented. The algorithm has been extensively tested on a shared-cache multi-core platform and a sketch proof of correctness is presented. The queues proposed have been used as basic building blocks to implement the FastFlow parallel framework, which has been demonstrated to offer very good performance for fine-grain parallel applications. © 2012 Springer-Verlag.