P300 investigation of phoneme change detection in dyslexic adults

A specific impairment in phoneme awareness has been hypothesized as one of the current explanations for dyslexia. We examined attentional shifts towards phonological information as indexed by event-related potentials (ERPs) in normal readers and dyslexic adults. Participants performed a lexical decision task on spoken stimuli of which 80% started with a standard phoneme and 20% with a deviant phoneme. A P300 modulation was expected for deviants in control adults, indicating that the phonological change had been detected. A mild and right-lateralized P300 was observed for deviant stimuli in controls, but was absent in dyslexic adults. This result suggests that dyslexic adults fail to make shifts of attention to phonological cues in the same way that normal adult readers do. (C) 2003 Elsevier Ireland Ltd. All rights reserved.

MSGR-based Low Latency Complex Matrix Inversion Architecture

This paper presents a matrix inversion architecture based on the novel Modified Squared Givens Rotations (MSGR) algorithm, which extends the original SGR method to complex valued data, and also corrects erroneous results in the original SGR method when zeros occur on the diagonal of the matrix either initially or during processing. The MSGR algorithm also avoids complex dividers in the matrix inversion, thus minimising the complexity of potential real-time implementations. A systolic array architecture is implemented and FPGA synthesis results indicate a high-throughput low-latency complex matrix inversion solution. © 2008 IEEE.

Generic low-latency NoC router architecture for FPGA computing systems

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems. © 2011 IEEE.

Rigorous Specification and Low-Latency Implementation of Technical Market Indicators

Technical market indicators are tools used by technical an- alysts to understand trends in trading markets. Technical (market) indicators are often calculated in real-time, as trading progresses. This paper presents a mathematically- founded framework for calculating technical indicators. Our framework consists of a domain specific language for the un- ambiguous specification of technical indicators, and a run- time system based on Click, for computing the indicators. We argue that our solution enhances the ease of program- ming due to aligning our domain-specific language to the mathematical description of technical indicators, and that it enables executing programs in kernel space for decreased latency, without exposing the system to users’ programming errors.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs

Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Size-assortative pairing in Gammarus pulex (Crustacea : Amphipoda): a test of the timing hypothesis

We present the first empirical test of the timing hypothesis regarding the generation of size-assortative pairing in amphipods. The timing hypothesis proposes that, since large males are better able to afford the costs of mate guarding than small males, the former can take larger females into precopula earlier in the female moult cycle than is feasible for the latter. This leaves small males to form pairs with smaller females closer to moult, thus generating size assortment. We presented male Gammarus pulex, collected both in precopula and as singletons, with females that were (1) previously guarded and therefore near to copulatory moult and (2) previously unguarded and therefore far from copulatory moult. This comparison tested the prediction of the timing hypothesis, that size assortment should break down when the opportunity for time-based male decisions is removed, but that size assortment should occur where timing is not disrupted. Counter to the hypothesis, we found that size assortment did not break down upon removal of the time factor. Large males tended to initiate mate guarding earlier than small males in both female moult groups. However, only in the previously unguarded group did large males guard for longer than small males. This result suggests that, although size assortment occurred in all groups, the causative mechanisms that generated this pattern may differ between these groups. We therefore consider the possible importance of mechanisms such as aggression, simultaneous manipulation of females and female resistance in producing size assortment where males encounter numerous females that are close to moult. We also observed that prior recent guarding experience by males had no effect on latency to guard or size-assortative pairing. (C) 2002 The Association for the Study of Animal Behaviour. Published by Elsevier Science Ltd. All rights reserved.