FPGA Soft-core Processors, Compiler and Hardware Optimizations validated using HOG

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Plasma power measurement and hysteresis in the E-H transition of a rf inductively coupled plasma system

An experimental investigation of the argon plasma behavior near the E-H transition in an inductively coupled Gaseous Electronics Conference reference cell is reported. Electron density and temperature, ion density, argon metastable density, and optical emission measurements have been made as function of input power and gas pressure. When plotted versus plasma power, applied power corrected for coil and hardware losses, no hysteresis is observed in the measured plasma parameter dependence at the E-H mode transition. This suggests that hysteresis in the E-H mode transition is due to ignoring inherent power loss, primarily in the matching system.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

‘5 ways to say your prayers’:The Art and Architecture of Curating People, Place and Creativity in a Post-Conflict Context. The Shed, Galway, Ireland 18th June – 23rd July 2013 Includes: 1. Co-Curation of Exhibition with Peter Mutschler, Director of PS² and 2. Morrow’s individual work as part of the exhibition, entitled ‘Departures & Arrivals: Academic Interactions with the Activities, Artists and Archive of PS² ’

This exhibition profiles the curatorial approach of PS² and the work of creative practitioners who have practiced alongside and with the organisation. PS² is a Belfast-based, voluntary arts organisation that initiates projects inside and outside its project space. It seeks to develop a socio-spatial practice that responds to the post-conflict context of Northern Ireland, with particular focus on active intervention and social interaction between local people, creative practitioners, multidisciplinary groups and theorists.
Morrow has collaborated with PS² since its inception in 2005, acting as curatorial advisor specifically on the projects that occur outside PS² . She regards her involvement as a parallel action to her pedagogical explorations within architectural education.

Morrow's personal contribution to the Exhibition aimed to:
-interrogate PS² spatial projects
-contextualise PS² curatorial practice
-open up the analytical framework and extend to similar local practices

The Shed, Galway, Ireland is a joint Galway City Arts and Harbour Company venture. The exhibition subsequently travelled to DarcSpace Gallery, Dublin (Sept 2013).

Fault Diagnostics for Internal Combustion Engines – Current and Future Techniques

The adoption of each new level of automotive emissions legislation often requires the introduction of additional emissions reduction techniques or the development of existing emissions control systems. This, in turn, usually requires the implementation of new sensors and hardware which must subsequently be monitored by the on-board fault detection systems. The reliable detection and diagnosis of faults in these systems or sensors, which result in the tailpipe emissions rising above the progressively lower failure thresholds, provides enormous challenges for OBD engineers. This paper gives a review of the field of fault detection and diagnostics as used in the automotive industry. Previous work is discussed and particular emphasis is placed on the various strategies and techniques employed. Methodologies such as state estimation, parity equations and parameter estimation are explained with their application within a physical model diagnostic structure. The utilization of symptoms and residuals in the diagnostic process is also discussed. These traditional physical model based diagnostics are investigated in terms of their limitations. The requirements from the OBD legislation are also addressed. Additionally, novel diagnostic techniques, such as principal component analysis (PCA) are also presented as a potential method of achieving the monitoring requirements of current and future OBD legislation.

Hardware Acceleration of Background Modeling in the Compressed Domain

In intelligent video surveillance systems, scalability (of the number of simultaneous video streams) is important. Two key factors which hinder scalability are the time spent in decompressing the input video streams, and the limited computational power of the processor. This paper demonstrates how a combination of algorithmic and hardware techniques can overcome these limitations, and significantly increase the number of simultaneous streams. The techniques used are processing in the compressed domain, and exploitation of the multicore and vector processing capability of modern processors. The paper presents a system which performs background modeling, using a Mixture of Gaussians approach. This is an important first step in the segmentation of moving targets. The paper explores the effects of reducing the number of coefficients in the compressed domain, in terms of throughput speed and quality of the background modeling. The speedups achieved by exploiting compressed domain processing, multicore and vector processing are explored individually. Experiments show that a combination of all these techniques can give a speedup of 170 times on a single CPU compared to a purely serial, spatial domain implementation, with a slight gain in quality.

Tools and Environments for Networked Electronic Performance

A collection of software and hardware tools and environments that facilitate collective networked performance between electronic musicians. Tools include 'Chat Monkey', a live chat tool for performance, 'DMA Sequencing', a step sequencer using open sound control messaging and multi nodal control, 'tutti, duet, trio, solo, quartet', an ensemble management environment, and 'Por Larrañaga', a cigar box based electro-acoustic instrument with embedded sensors and controllers. Notable performances: w/BLISS, NCAD, Dublin, 1 March 2015; w/BLISS, NI Science Festival, Belfast, 21 Feb 2015

WLAN Security Processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures. © 2006 IEEE.

Do benchmark African equity indices exhibit the stylized facts?

This paper investigates if benchmark African equity indices exhibit the stylized facts reported for financial time-series returns. The returns distributions of the Africa All-Share, Large, Medium and Small Company Indices were found to be leptokurtotic, had fat-tails, over time experienced volatility clustering and exhibited long memory in volatility. Both the All-Share and Large Company Indices were found to exhibit leverage effects. In contrast, positive shocks had a greater impact on future volatility for the Small Company Index which implies a reverse leverage effect. This finding could reflect a bull/bubble market for small capitalisation stocks in Africa.

Core-based Methodology: An Automated Approach for Implementing a Complete System From Algorithms to a Heterogeneous Network Including FPGAs

In this paper, we present a methodology for implementing a complete Digital Signal Processing (DSP) system onto a heterogeneous network including Field Programmable Gate Arrays (FPGAs) automatically. The methodology aims to allow design refinement and real time verification at the system level. The DSP application is constructed in the form of a Data Flow Graph (DFG) which provides an entry point to the methodology. The netlist for parts that are mapped onto the FPGA(s) together with the corresponding software and hardware Application Protocol Interface (API) are also generated. Using a set of case studies, we demonstrate that the design and development time can be significantly reduced using the methodology developed.